Efficient Full Adder Design Based on New Reversible Tuned Fredkin Gate (TFG)

Reversible logic is becoming one of the highlights of innovative research trends in recent times. It has proved to be a promising candidate for the applications in nanotechnology, quantum computations, and low-power CMOS devices. The need for miniaturization and low power electronics is an ever-emerging research area in lowering power consumption and heat dissipation. In this paper, we are introducing an efficient design approach for a reversible full-adder. This is achieved by introducing a new universal gate called Tuned Fredkin Gate (TFG), which is able to synthesize any Boolean function. Quantum realization of Feynman, Fredkin, and also TFG gate is presented here. The proposed full-adder design outperforms various existing designs based on quantum measures like quantum cost (QC), ancilla inputs (Constant inputs), garbage outputs (GO), and delay. It has shown a reduction in quantum cost by 1 unit, in constant input by 100%, in garbage output by 50%, and in delay by two gate counts. The performance analysis was carried out in Xilinx Vivado 2016.1 environment using Verilog. Moreover, the simplicity in the design structure compared with the existing counterparts makes it a viable choice over other existing ones.