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Erschienen in:
1988 | OriginalPaper | Buchkapitel
Electrical and Interface Properties of MOS Structures of Getter Treated Silicon
verfasst von : N. M. Ravindra, Patrick Smith, J. Narayan
Erschienen in: The Physics and Technology of Amorphous SiO2
Verlag: Springer US
Enthalten in: Professional Book Archive
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Electrical and micro-structural properties of Metal-Oxide-Semiconductor (MOS) capacitors fabricated utilizing silicon wafers, treated differently for gettering of impurities, is reported in this study. The treatment of silicon wafers for gettering purposes, considered here, essentially involves (i) back side argon ion implantation at doses of 2.5 × 1015 cm-2 and 5.0 × 1015 cm-2, at energies of 195 and 350 keV respectively, and (ii) back side polysilicon deposition. The results of these measurements have been compared with those of ungettered silicon. Results indicate that some improvement has been attained in minority carrier lifetimes and maximum breakdown voltages in MOS capacitors fabricated particularly using back side argon ion implanted silicon.