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Erschienen in:
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2014 | OriginalPaper | Buchkapitel

11. Encoder Hardware Architecture for HEVC

verfasst von : Sung-Fang Tsai, Cheng-Han Tsai, Liang-Gee Chen

Erschienen in: High Efficiency Video Coding (HEVC)

Verlag: Springer International Publishing

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Abstract

In this chapter, an encoder hardware architecture design for HEVC is described. The system pipeline is first introduced followed by the design details of the different HEVC encoder modules such as inter prediction, intra prediction, mode decision, in-loop filters, and entropy coding. Finally, a sample test chip implementation result is presented as a reference.

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Vorheriges Kapitel Decoder Hardware Architecture for HEVC
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Metadaten
Titel
Encoder Hardware Architecture for HEVC
verfasst von
Sung-Fang Tsai
Cheng-Han Tsai
Liang-Gee Chen
Copyright-Jahr
2014
Buch
High Efficiency Video Coding (HEVC)

Print ISBN: 978-3-319-06894-7

Electronic ISBN: 978-3-319-06895-4

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-06895-4_11

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