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Erschienen in:
Improving Non-profiled Attacks on Exponentiations Based on Clustering and Extracting Leakage from Multi-channel High-Resolution EM Measurements Kapitel lesen Erstes Kapitel lesen

2015 | OriginalPaper | Buchkapitel

Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs

verfasst von : Alexander Wild, Amir Moradi, Tim Güneysu

Erschienen in: Constructive Side-Channel Analysis and Secure Design

Verlag: Springer International Publishing

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Abstract

Power-equalization schemes for digital circuits aim to harden cryptographic designs against power analysis attacks. With respect to dual-rail logics most of these schemes have originally been designed for ASIC platforms, but much efforts have been spent to map them to FPGAs as well. A particular challenge is here to apply those schemes to the predefined logic structures of FPGAs (i.e., slices, LUTs, FFs, and routing switch boxes) for which special tools are required. Due to the absence of such routing tools Yu and Schaumont presented the idea of duplicating (i.e., dualizing) a fully-placed-and-routed dual-rail precharge circuit with equivalent routing structures on an FPGA. They adopted such architecture from WDDL providing the Double WDDL (DWDDL) scheme.
In this work we show that this general technique – regardless of the underlying dual-rail logic – is incapable to properly prevent side-channel leakages. Besides theoretical investigations on this issue we present practical evaluations on a Spartan-6 FPGA to demonstrate the flaws in such an approach. In detail, we consider an AES-128 encryption module realized by three dual-rail precharge logic styles as a case study and show that none of those schemes can provide the desired level of protection.

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Vorheriges Kapitel Two Operands of Multipliers in Side-Channel Attack
Nächstes Kapitel Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware
Fußnoten
1
Note that such a selection should also be randomized.
 
2
One reason is also related to the static leakage [13].
 
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Metadaten
Titel
Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs
verfasst von
Alexander Wild
Amir Moradi
Tim Güneysu
Copyright-Jahr
2015
Buch
Constructive Side-Channel Analysis and Secure Design

Print ISBN: 978-3-319-21475-7

Electronic ISBN: 978-3-319-21476-4

Copyright-Jahr: 2015

DOI
https://doi.org/10.1007/978-3-319-21476-4_6

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