Computed tomography (CT) is a widely used imaging technique in the field of medical diagnosis and industrial non-destructive testing (NDT) applications. Using a sufficiently large series of X-ray images taken from different views around the object or patient a digital computer is used to generate slice images of the inside of the considered object or patient.
There exist several reconstruction methods for computing a volumetric representation of a scanned object from a set of two-dimensional X-ray projection images. However, the most commonly applied method in practical cone-beam CT systems is the approximate FDK method. After we give some prerequisites that are necessary to understand the following descriptions, we present in Section 2.2 the FDK method, discuss possible implementation strategies (Section 2.2.2) that can be applied to practical cone-beam systems and analyze the time complexity of the involved algorithmic steps (Section 2.2.3).
The design and implementation of the reconstruction system in medical X-ray imaging is a challenging issue due to its immense computational demands. In order to ensure an efficient clinical workflow it is inevitable to meet high performance requirements. Hence, the usage of hardware acceleration is mandatory. The software architecture of the reconstruction system is required to be modular in a sense that different accelerator hardware platforms are supported. It must be possible to implement different parts of the algorithm using different acceleration architectures and techniques.
Long before other microprocessor chip vendors developed wide spread multi-core processors Sony Computer Entertainment, Toshiba, and IBM formed an allegiance (commonly known as STI-allegiance) to build a highly multi-core processor that can overcome the problems of traditional microprocessor technology. The outcome was the Cell Broadband Engine Architecture [Cell 06, Pham 05] which mainly targets three different market shares. The first major commercial application of the Cell processor was Sony's activity to penetrate the gaming market with the Cell-based PlayStation 3 video game console. Further application domains of the Cell processor are in the multimedia industry and in the high performance computing community. For example, IBM's latest supercomputer, the IBM Roadrunner, is a hybrid system consisting of General Purpose CISC Opteron processors as well as PowerXCell 8i Cell processors. In June 2008 this supercomputer ranked first in the TOP500 list, which maintains the list of the world's most powerful supercomputers, reaching record-breaking one Petaflop – a quadrillion floating-point operations per second – of compute power using the standard Linpack benchmark.
For a long time, the performance of general-purpose processors could be improved by increasing clock frequency and instruction level parallelism (ILP). Nowadays, only diminished gains in performance can be reached by higher processor clock rates. This results from the difficulty to find enough parallelism in the instruction stream of a single process to keep higher performance processor cores busy. Another cause is the increasing gap between processor and main memory speed because the latency and the bandwidth of dynamic random access memory (DRAM) does not improve accordingly to processor operating frequencies. Finally, higher clock rates of generalpurpose processors lead to dramatically increased problems in manufacturing, system design, and deployment. These three arguments, commonly referred to as the ILP wall, the memory wall and the power wall, respectively, have constituted much of the motivation for the advent of multi-core processors during the last few years.
While graphics accelerator boards are traditionally built for the gaming industry, nowadays these devices are usable for general computing tasks as well. GPUs are specialized for compute-intensive, highly parallel computations. In contrast to standard multi- or many-core architectures much more transistors are implemented for data processing rather than data caching and flow control. Hence, it is very appealing to use these architectures as acceleration platform for high-performance computing tasks in medical devices.
Besides off-the-shelf graphics cards, reconfigurable hardware has been gaining attention in the field of massively parallel high-performance computing as well. Several computer manufacturers offer FPGA-based accelerator components together with dedicated libraries in order to speed up the execution of numerically intensive codes. Such hardware components are particularly appropriate for applications in the signal processing domain such as image or video compression, for instance.
Although many CT systems use the FDK method to solve the 3-D image reconstruction task, it is not without its short-comings. Therefore, we have described in Section 2.3 two alternative approaches: the theoretically exact and stable M-line method applied to a short-scan circle-plus-arc acquisition (Section 2.3.1) and the simultaneous algebraic reconstruction technique as a representative of the iterative approaches (Section 2.3.2).
This chapter summarizes the main contributions and results of this work and describes future directions for research in the field of hardware-accelerated cone-beam CT reconstruction.
Holger Scherl
Backmatter
Metadaten
Titel
Evaluation of State-of-the-Art Hardware Architectures for Fast Cone-Beam CT Reconstruction
verfasst von
Holger Scherl
Copyright-Jahr
2011
Verlag
Vieweg+Teubner
Electronic ISBN
978-3-8348-8259-2
Print ISBN
978-3-8348-1743-3
DOI
https://doi.org/10.1007/978-3-8348-8259-2
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