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Erschienen in:
A Power-Optimized High-Speed and High-Resolution Pipeline ADC with a Parallel Sampling First Stage for Broadband Multi-Carrier Systems Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

6. Event-Driven Successive Charge Redistribution Schemes for Clockless Analog-to-Digital Conversion

verfasst von : Dariusz Kościelnik, Marek Miśkowicz

Erschienen in: Design, Modeling and Testing of Data Converters

Verlag: Springer Berlin Heidelberg

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Abstract

The analog-to-digital conversion methods based on event-driven successive charge redistribution schemes are presented in the study. In the proposed schemes, the charge redistribution is forced by a self-timed mechanism that substitutes a clock in driving a converter operation. One of important implications is that the converter almost does not consume energy in breaks between conversion cycles that can be triggered irregularly in time.

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Vorheriges Kapitel Incremental and Extended-Range Data Converters
Nächstes Kapitel Time-to-Digital Converters
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Metadaten
Titel
Event-Driven Successive Charge Redistribution Schemes for Clockless Analog-to-Digital Conversion
verfasst von
Dariusz Kościelnik
Marek Miśkowicz
Copyright-Jahr
2014
Verlag
Springer Berlin Heidelberg
Buch
Design, Modeling and Testing of Data Converters

Print ISBN: 978-3-642-39654-0

Electronic ISBN: 978-3-642-39655-7

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-642-39655-7_6

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