Evolvable Systems: From Biology to Hardware

An evolvable hardware (EHW) system for high-speed sonar return classification has been proposed. The system demonstrates an average accuracy of 91.4% on a sonar spectrum data set. This is better than a feed-forward neural network and previously proposed EHW architectures. Furthermore, this system is designed for online evolution. Incremental evolution, data buses and high level modules have been utilized in order to make the evolution of the 480 bit-input classifier feasible. The classification has been implemented for a Xilinx XC2VP30 FPGA with a resource utilization of 81% and a classification time of 0.5

μ

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Automatic design of electronic logic circuits has become a new research focus with the cooperation of FPGA technology and intelligent algorithms in recent twenty years. However, as the size of logic circuits became larger and more complex, it has become difficult for the automatic design method to obtain valid and optimized circuits. Based on a divide-and-conquer approach, a two-layer encoding scheme was devised for design of electronic logic circuits. In the process of evolvement, each layer was evolved parallel and they contacted each other at the same time. Moreover, in order to simulate and evaluate evolved electronic logic circuits, a two-step simulation algorithm was proposed to reduce computation complexity of simulating circuits and to improve the simulation efficiency. At last, a random number generator was automatically designed with this encoding scheme and the proposed simulation algorithm, and the result showed this method was efficient.

To conquer the scalability issue of evolvable hardware, this paper proposes a multi-virtual reconfigurable circuit (VRC) cores-based evolvable system to evolve combinational logic circuits in parallel. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several sub-circuits, and each of them is evolved independently as a subcomponent by its corresponding VRC core. The virtual reconfigurable circuit architecture is designed for implementing real-world applications of evolvable hardware (EHW) in common FPGAs. In our approach, all the VRC cores are realized in a Xilinx Virtex xcv2000E FPGA as an evolvable system to achieve parallel evolution. The proposed method is evaluated on the evolutions of 3-bit multiplier and adder and compared to direct evolution and incremental evolution in the terms of computational effort and hardware implementation cost.

In traditional, designing analog and digital electrical circuits are the tasks of hard engineering, but with the emergence of Evolvable Hardware (EHW) and many researchers’ significant research in this domain, EHW has been established as a promising solution for automatic design of digital and analog circuits during the last 10-odd years. At present, the main research in EHW field is focused on the extrinsic and intrinsic evolution. In this paper, we will fix our attention on intrinsic evolution. Some researchers concentrate on how to implement intrinsic evolution, mainly including the following three aspects: The first, evolve the bitstream directly and then recompose the bitstream; The second, amend the content of Look-Up-Table (LUT) by relative tools; The third, set up a virtual circuit on a physical chip, and then evolve its “parameters” which are defined by the deviser, when the parameters are changed, the corresponding circuit is evolved. This paper ignores the first and the second approaches, and proposes a virtual circuit based on Multiplexer Module Array (MMA) which is implemented on a Xilinx Virtex-II Pro (XC2VP20) FPGA.

Array connectivity is an important feature for measuring the efficiency of evolution. Generally, the connectivity is estimated by array geometry and level-back separately. In this paper, a connectivity model based on the path number between the first node and the last node is esteblished. With the help of multinomial coefficient expansion, a formula for estimating array connectivity is presented. By applying this technique, the array geometry and level-back are taken into account simultaneously. Comparison of connectivity within arrays of different geometries and level-backs becomes possible. Enlightened by this approach, a multi-output node structure is developed. This structure promotes the connectivity without increasing the array size. A multi-objective fitness funciton based on power consumption and critical delay of circuits is proposed, which enables evolved circuits to agree with the requirements of applications. Experimental results show that the proposed approach offers flexibility in constructing circuits and thus improves the efficiency of evolutionary design of circuits.

An issue that arises in evolvable hardware is how to verify the correctness of the evolved circuit, especially in online evolution. The traditional exhaustive evaluation approach has made evolvable hardware unpractical to real-world applications. In this paper an incremental evaluation approach for online evolution is proposed, in which the immune genetic algorithm is used as the search engine. This evolution approach is performed in an incremental way: some small seed-circuits have been evolved firstly; then these small seed-circuits are employed to evolve larger module-circuits; and the module-circuits are utilized to build still larger circuits further. The circuits of 8-bit adder, 8-bit multiplier and 110-sequence detector have been evolved successfully. The evolution speed of the incremental evaluation approach appears to be more effective compared with that of the exhaustive evaluation method; furthermore, the incremental evaluation approach can be used both in the combinational logic circuits as well as the sequential logic circuits.

A novel multi-objective evolutionary mechanism for digital circuits is proposed. Firstly, each CLB of FPGA is configured as minimum evolutionary structure cell (MESC). The two-dimensional array consisted of MESCs by integer scale values is coded. And the functions and interconnections of MESCs are reconfigured. Secondly, the circuit function, the number of active CLBs and the circuit response speed are designed for evolutionary aims. The fitness of the circuit function is evaluated by on-line test. The fitness of the active CLBs’ number and response speed are evaluated by searching the evolved circuit in reverse direction. Then the digital circuits are designed by multi-objective on-line evolution in these evaluation methods. Thirdly, a multi-objective optimization algorithm is improved, which could quicken the convergence speed of on-line evolution. Finally, Hex-BCD code conversion circuit is taken as an example. The experimental results prove the feasibility and availability of the new on-line design method of digital circuits.

Combinational multipliers represent a class of circuits that is usually considered to be hard to design by means of the evolutionary techniques. However, experiments conducted under the previous research demonstrated (1) a suitability of an instruction-based developmental model to design generic multiplier structures using a parametric approach, (2) a possibility of the development of irregular structures by introducing an environment which is considered as an external control of the developmental process – inspired by the structures of conventional multipliers and (3) an adaptation of the developing structures to the different environments by utilizing the properties of the building blocks. These experiments have represented the first case when generic multipliers were designed using an evolutionary algorithm combined with the development. The goal of this paper is to present an improved developmental model working with the simplified building blocks based on the concept of conventional generic multipliers, in particular, adders and basic AND gates. We show that this approach allows us to design generic multiplier structures which exhibit better delay in comparison with the classic multipliers, where adder represents a basic component.

This paper proposes a new method to synthesize practical passive filter using Clonal Selection principle-based Gene Expression Programming and binary tree representation. The circuit encoding of this method is simple and efficient. Using this method, both the circuit topology and component parameters can be evolved simultaneously. Discrete component value is used in the algorithm for practical implementation. Two kinds of filters are experimented to verify the excellence of our method, experimental results show that this approach can generate passive RLC filters quickly and effectively.

For electronic devices especially used in extreme-environment, it is very important to ensure high-reliability and long-lifetime operation; so it is significant to develop fault-tolerant mechanisms by adopting evolutionary algorithm. Based on EHW (evolvable hardware), this paper presents a new FPACA (field programmable analog cell array) which is an evolution-oriented reconfigurable architecture and can implement evolution of both analog and digital functions. Adopting single-chromosome evolutionary algorithm, we establish evolutionary reconfiguration mechanism to research the fault- tolerance of evolutionary analog circuits, such as amplifiers, filters or DAC (digital to analog converters). Comparing to FPTA, FPACA has the advantages of low hardware cost and convenience of software analysis and simulation. By implementing a typical amplifier circuit, we illustrate the fault-tolerance of FPACA analog circuits and the experimental results show the correctness and feasibility of FPACA.

FPTA-2 with feedback structure is evolved to achieve an effective amplifier. Results in both time and frequency domain show it’s more effectively than using open-loop circuit. A new kind of fitness function based on square error threshold is put forward. Special points of sine wave can evolve better by using such evaluation function. A new structure of multi-cell circuits is designed and experiments show such new structure can make evolution easier.

In the complex information environment, the role of intelligent system is getting high and it is essential to develop a smarter and more efficient intelligent system for processing automatic knowledge acquisition, structuring the memory efficient to store and retrieving the related information and repairing the system automatically. Focusing on the self repairing system, in this study Medicine Self Repairing Strategy for knowledge network management is designed. The concepts of Self type, Internal Entropy, medicine treatment are defined for modeling Self Repairing System. We applied this proposed system to virtual memory consisting of knowledge network and tested the results.

This paper presents a new design of cells to construct embryonic arrays, the function unit of which can act in three different operating modes. Compared with cells based on LUT with four inputs and one output, the new architecture displays improved flexibility and resource utilization ratios. Configuration memory employed by embryonics can implement 1-bit error correcting and 2-bit error checking by using extended hamming code. The two-level fault-tolerance is achieved in the embryonic array by the error correcting mechanism of memory at cell-level and column-elimination mechanism at array-level which is triggered by cell-level fault detection. The implementation and simulation of a 4-bit adder subtracter circuit is presented as a practical example to show the effectiveness of embryonic arrays in terms of functionality and two-level fault-tolerance.

Due to the generic and highly programmable nature, gate-based FPGA provides the ability to implement a wide range of application. However, its small cell and complex interconnection network cause problems of low hardware resource utilization ratio and long interconnection time-delay in compute-intensive information processing field. PMAC (Programmable Multiply-Add Cell) presented in this article ensures high-speed and flexibility by adding much programmability to the multiply-add structure. PMAC array architecture resolves these problems and greatly increases resource utilization ratio and the efficiency of information processing. By establishing PMAC model and simulating, PMAC array is actualized on the VirtexII Pro series XC2VP100 device. By implementing FFT butterfly operation and 4

th

order FIR on PMAC array, flexibility and correctness of the architecture are proved. The results have also shown to have an average increase of 28.3% in resource utilization ratio and decrease of 15.5% in interconnection time-delay.

Bio-inspired systems borrow three structural principles characteristic of living organisms: multicellular architecture, cellular division, and cellular differentiation. Implemented in silicon according to these principles, our cellular systems are endowed with self-developing mechanisms like configuration, cloning, cicatrization, and regeneration. These mechanisms are made of simple processes such as growth, load, branching, repair, reset, and kill. The hardware simulation and hardware implementation of the self-developing mechanisms and their underlying processes constitute the core of this paper.

This paper describes an on-going research to develop a Brain-Computer Interface (BCI) with which to conduct biofeedback training. A convenient portable wireless two-channel tiny Electroencephalogram (EEG) acquisition device has been developed for this study, which is based on Radio Frequency (RF) technology, and we developed a computer assisted EEG biofeedback system using Virtual Reality which provides an ideal medium to represent the spatial and temporal environment of electrical activity emanating from the brain. A system prototype system has been implemented with the proposed device for attention enhancement training with Virtual Reality (VR) environment, and 3 volunteers’ test results are reported in this paper. With the proposed system, lots of EEG biofeedback training can be designed easily and done at home in our daily life conveniently.

EHW is the acronym used to denote an emerging and relatively new research field in digital hardware design; it stands for Evolvable Hardware. This technique has attracted many researchers since the 1990’s. EHW aims at an automatic design and optimisation of a reconfigurable hardware system using Evolutionary Algorithms (EAs), such as Genetic Algorithms, Genetic programming etc. This article is published as part of a three years research project. The objective of this project is to employ the above method on a target specific hardware, the Embryonics Hardware System. The latter requires large hardware resources. Thus, in this project, EAs will be used to evolve the Embryonics Hardware System to discover novel design with reduced complexity. The new design must first ensure the correct functionality. Hence to verify the concept of Evolvable Hardware, the authors, in this paper, focus on the design of relatively simple combinatorial logic circuits using Genetic Algorithms with multi-objective fitness.

This paper presents elementary circuit components which exhibit self-checking properties; however, which do not utilize any additional signals to indicate the fault. The fault is indicated by generating specific values at some of standard outputs of a given circuit. In particular, various evolved adders containing conventional as well as polymorphic gates are proposed with less than duplication overhead which are able to detect a reasonable number of stuck-at-faults by oscillations at the carry-out output when the control signal of polymorphic gates oscillates.

Electronic systems with intrinsic adaptive and evolvable features can potentially significantly increase functionality of a system. To achieve high level of adaptivity the system must be able to modify its internal configuration under changing environmental conditions without interrupting operation. This can be achieved through dynamic reconfiguration. Dynamic reconfiguration of arrays of processors often relies on the specialized architectures with the built-in reconfiguration capacities. Specialized architectures suffer from lack of flexibility and high cost. Reconfiguration algorithms for highly practical general purpose architectures such as rectangular grid of processors are highly complex and, thus, unsuitable for dynamic reconfiguration. This paper proposes a systematic approach to reconfigurable architectures. The general framework for reconfiguration algorithms design is presented based on discrete Morse functions and discrete vector fields on cellular complexes.

The precision and power consumption of pipelined FFT processors are highly affected by the wordlengths in fixed-point application systems. Due to nonconvex space, wordlength optimization under multiple competing objectives is a complex, time-consuming task. This paper proposes a new approach to solving the multi-objective evolutionary optimization design of pipelined FFT processors for wireless OFDM receivers. In our new approach, the number of design variables can be significantly reduced. We also fully investigate how the internal wordlength configuration affects the precision and power consumption of the FFT by setting the wordlengths of input and FFT coefficients to be 12 and 16 bits in fixed-point number type. A new system-level model for representing power consumption of the pipelined FFT is also developed and utilized in this paper. Finally, simulation results are provided to validate the effectiveness of applying the nondominated sorting genetic algorithm to the multi-objective evolutionary design of a 1024-point pipelined FFT processor for wireless OFDM receivers.

An evolutionary algorithm is utilized to find a set of image filters which can be employed in a bank of image filters. This filter bank exhibits at least comparable visual quality of filtering in comparison with a sophisticated adaptive median filter when applied to remove the salt-and-pepper noise of high intensity (up to 70% corrupted pixels). The main advantage of this approach is that it requires four times less resources on a chip when compared to the adaptive median filter. The solution also exhibits a very good behavior for the impulse bursts noise which is typical for satellite images.

In this paper, the concept of evolution is introduced to examine the generation process for Walsh function systems. By considering the generation process for Walsh function systems as the evolution process of certain discrete dynamic systems, a new unified generation pattern which is called the Bisectional Evolutional Generation Pattern (BEGP for short) for Walsh function systems is proposed, combined with their properties of symmetric copying. As a byproduct of this kind of pattern, a kind of ordering for Walsh function systems which is called quasi-Hadamard ordering is found naturally.

The RISA Architecture is a novel reconfigurable hardware platform containing both hardware and software reconfigurable elements. This paper describes the architecture and the features that make it suitable for implementing biologically inspired systems such as the evolution of digital circuits. Some of the architecture’s capabilities are demonstrated with the results of evolving a simple combinatorial circuit using one of the fabricated RISA devices.

Fault Tolerance is an increasing challenge for integrated circuits due to semiconductor technology scaling. This paper looks at how artificial evolution may be tuned to the creation of novel redundancy structures which may be applied to meet this challenge. An experimental setup and results for creating “useful” redundant structures is presented.

Underwater acoustic channel (UACh) requires robust techniques to get high speed data transmission for reliable communication. If the channel can be estimated and this estimate sent back to the transmitter, the transmission scheme can be adapted to the channel variation. In this paper, we assume a fixed source and receiver configuration over a slowly-varying UACh, where the instantaneous signal to noise ratio (SNR) is constant over a large number of transmissions and then changes to a new value based on the Rayleigh fading distribution. Theoretical derivation of channel capacity (ChC) shows that we can optimize the data rate allowing the transmit power to vary with SNR, subject to an average power constraint. Simulation study also shows that using adaptive technique, we can adapt the channel variation in UACh communication. We also find that variability of the UACh capacity seems not to be negligible by the sloping condition.

This paper addresses a new approach to navigate mobile robot in static or dynamic surroundings based on particle swarm optimization (PSO) and stream functions (or potential flows). Stream functions, which are introduced from hydrodynamics, are employed to guide the autonomous robot to evade the obstacles. PSO is applied to generate each optimal step from initial position to the goal location; furthermore, it can solve the stagnation point problem that exists in potential flows. The simulation results demonstrate that the approach is flexible and effective.

This paper presents an adaptive control system suitable for the control technology of BTT-45 air-to-air missile. It resolves a problem of the BTT-45 missile’ channel coupling through the application of the idea which is similar to “reversing design”. The proposed system has the following features: (1)Adaptive robust control; (2)Self-decoupling. A simulation example is used to demonstrate excellent performance of the proposed system.

This paper argues in favor of evolvable hardware as a technique to improve the capability of on-board computers for deep space exploration. From architecture point of view, it analyzes the role of EHW in the multi-level structure of the intelligent system and describes the two mainly characters of the computer system building with EHW. It emphasizes the important of supercomputing capability and self-determination ability. In order to illuminate the implementation of an evolvable computer system, it describes a demo structure for object recognition that realizes image-matching function for space application.

Biological organisms have an inherent ability to respond to environmental changes. The response can emerge as organisms that can develop to structural and behavioural different phenotypes. The cue to what phenotypic property to express is cued by the environment. This implies that the information necessary for a single genotype to develop to different phenotypes is the genome itself and the information provided by the environment i.e. phenotypic plasticity. This concept is incorporated in the development model presented herein so as to demonstrate how an evolved genome can express different phenotypes depending on the present environment which the phenotype has to develop and survive in. An experimental approach is used to show the concept to evolved robust behaviour in different environments and to evolve genomes that can be triggered to express different behaviour depending on the present environment.

Passive Power Filters (PPFs) are vital equipments for harmonic pollution control, but optimal design of PPFs is a rather difficult problem of multi-objective optimization and evaluation. On the basis of our previous work in evolvable hardware, especially evolutionary design of circuits, a Uniform Design Technique (UDT) based multi-objective genetic algorithm was developed towards optimal design of PPFs. It is characterized by an efficient and effective encoding-decoding scheme based on the standard series of component values, a mechanism to integrate and evaluate multi-objectives based on UDT, weight-vectors adjusting and PSpice simulation, a UDT based multi-parent crossover operator to improve offspring quality and computation cost, and an adaptation technique for genetic parameters to maintain the individual diversity and track the GA process. It is shown by simulation results capable of searching out a set of effective design results of PPFs, which meet the main optimization objectives and reflect roughly interactions between them.

A major bottleneck in the evolutionary design of electronic circuits is the problem of scale. This refers to the very fast growth of the number of gates, used in the target circuit, as the number of inputs of the evolved logic function increases. Another related obstacle is the time required to calculate the fitness value of a circuit. In this paper, We propose a new means (Gene Expression Programming) for designing electronic circuits and introduces the encoding of the circuit as a chromosome, the genetic operators and the fitness function. From the case studies show this means has proved to be efficient to the electronic circuit and the evolution speed is fast .The experiments results show that we have attained the better results.

Polymorphic circuit is a kind of multifunctional circuits that can perform two or more functions under different conditions. And those functions can be activated by changing control parameters, such as temperature, power supply voltage, illumination and so on. Polymorphic circuit provides a novel approach to build multifunctional circuits, and it can be used in many fields. However, polymorphic circuit can not be designed with conventional methods and is hard to be evolved with evolutionary algorithms directly. A novel evolutionary algorithm based on the weighted sum method is proposed in this paper, which can be used to evolve polymorphic circuits at gate level. The experimental results demonstrate that this algorithm can increase the success ratio and decrease the evolutionary generations needed to evolve a polymorphic circuit.

The adjustment of optical axes is crucial for laser systems. We have previously proposed an automatic adjustment method using genetic algorithms to adjust the optical axes. However, there were still two problems that needed to be solved: (1)long adjustment times, and (2)adjustment precision due to observation noise. In order to solve these tasks, we propose a robust and efficient automatic multi-objective adjustment method using stochastic binary search algorithm. Adjustment experiments for optical axes with 4-DOF in noisy environment demonstrate that the proposed method can robustly adjust the positioning and the angle of the optical axes in about 12 minutes.

Most sensor networks are deployed with high density and then node duty cycle is dynamically managed in order to prolong the network lifetime. In this paper, we address the issue of maintaining sensing coverage of surveillance target in large density wireless sensor networks and present an efficient technique for the selection of active sensor nodes. First, the At Most k-Coverage Problem (AM k-Coverage) is modeled as a nonlinear integer programming. Then Genetic Algorithm is designed to solve the multi-objective nonlinear integer programming, which is a quasi-parallel method. And later by using Genetic Algorithm, a central algorithm is designed to organize a sensor network into coverage sets. Considering that the central base station consumes a great deal of energy when it collects the coverage information from every node, we also propose a localized manner on the basis of the proposed central algorithm. Finally, Experimental results show that the proposed algorithm can construct the coverage sets reliably and reduce the number of active sensor nodes which is helpful to reduce system energy consumption and prolong the network lifespan.

In this paper extended Hamming distance is introduced to construct the search space. According to the features of this space, a hierarchical mutation strategy is developed for the purpose of enlarging the search area with less computation effort. A local learning principle is proposed. This principle is used to ensure that no mutation operates on the same locus of chromosomes within one generation. An evaluation method called fitness effort for calculating computational effort per increased fitness value is also given. Experimental results show that the proposed hybrid approach of hierarchical mutation and local learning can achieve better performance than traditional methods.

Development of analog electronic solutions for space avionics is expensive and lengthy. Lack of flexible analog devices, counterparts to digital Field Programmable Gate Arrays (FPGA), prevents analog designers from rapid prototyping, and forces them to expensive custom design, fabrication, and qualification of application specific integrated circuits (ASIC). The limitation come from two directions: first, commercial Field Programmable Analog Arrays (FPAA) have little variability in the components offered on-chip; and second, these are only qualified for military grade temperatures, at best. However, more variability is needed for covering many sensing and control applications. Furthermore, in order to save mass, energy and wiring, there is strong interest in developing extreme environment electronics and avoiding thermal and radiation protection altogether. This means electronics that maintain correct operation while exposed to temperature extremes e.g., on Moon (-180°C to +125°C). This paper describes a recent version of a FPAA design, the JPL Self-Reconfigurable Analog Array (SRAA). It overcomes both limitations, offering a variety of analog cells inside the array together with the possibility of self-correction at extreme temperatures. A companion digital ASIC designed for algorithmic control, including a genetic algorithm implementation, is currently under fabrication.

Reconfigurable logic is a promising technology for adaptable systems – often called reconfigurable computing. However, one of the main challenges with autonomous adaptable systems is the flexibility. The paper starts with giving an overview of reconfigurable computing and different approaches to how it can be implemented. Then, we outline how these can be applied in on-line evolvable systems to improve flexibility in the hardware. The challenge of the latter is to include flexibility without re-synthesis and avoid having a too large logic gate overhead. An architecture based on system-on-chip and partial reconfiguration is proposed in the paper.

S-boxes constitute a cornerstone component in symmetric-key cryptographic algorithms, such as DES and AES encryption systems. In block ciphers, they are typically used to obscure the relationship between the plaintext and the ciphertext. Non-linear and non-correlated S-boxes are the most secure against linear and differential cryptanalysis. In this paper, we focus on a two-fold objective: first, we evolve regular an S-box with high non-linearity and low auto-correlation properties using evolutionary computation; then automatically generate evolvable hardware for the obtained S-box. Targeting the former, we use the Nash equilibrium-based multi-objective evolutionary algorithm to optimise regularity, non-linearity and auto- correlation, which constitute the three main desired properties in resilient S-boxes. Pursuing the latter, we exploit genetic programming to automatically generate the evolvable hardware designs of substitution boxes that minimise hardware space, encryption/decryption time and dissipated power, which form the three main hardware characteristics. We compare our results against existing and well-known designs, which were produced by using conventional methods as well as through evolution.

Constructing an evolutionary engine platform in evolvable hardware (EHW) is one of the most important topics, and a sophisticated architecture for the application of adaptive hardware is the key for the platform. In real world, most applications are multi-objective, and it is much necessary to solve the multi-objective problems (MOPs) by implementing evolutionary multi-objective optimization (EMO) in a special hardware platform. At present, there are far fewer attempts concerned with the theme. In this paper, we present an adaptive hardware platform to implement EMO algorithms utilizing high-performance digital signal processor (DSP) device. In this design, we mainly solve the problem of speedup in execution of evolutionary search by using parallel construct to implement such an EMO algorithm on DSP. Experimental results show that our platform works quite well. We still get a speedup of nearly 100 times in the condition that the CPU host frequency is 1810MHz and the hardware clock frequency is 150MHz, which offers an idea that by using a higher frequency DSP, we will get a better speedup, and we may further solve the real-world MOPs in real time.

Research in Evolutionary Computation has switched some of its focus to applications in Electrical Engineering problems, leading to the field of study called Evolvable Hardware (EHW). The final goal is the creation of complete evolvable hardware systems that can adapt to changing environments and increase system performance during operation. To accomplish this task, there are three main components in this system: Genetic Algorithm, response evaluation and configurable hardware. Though the interpretation of the binary chromosome will vary from one optimization problem to another, the manipulation of the chromosomes using reproduction operators such as crossover and mutation will stay consistent. In this paper, we design a hardware-based architecture to perform the Genetic Algorithm in this system, called FPGA-based Genetic Algorithm Kernel. This modular architecture of the Genetic Algorithm will ensure its ease for modifications and suitability for different applications.

The way combining intelligent technology with hardware technology to study real-world applications is one of the most important methodologies in the field of EHW. This paper designs a novel evolvable hardware engine for predictive lossless image compression in the perspective of hardware, and firstly implements the whole engine on reconfigurable hardware. As a result of the high-speed pipeline architecture, all the modules of this engine can process the data in parallel. For the most time-consuming fitness evaluation unit, the systolic array which essentially accelerate the fitness evaluation is employed. Experimental results show that the proposed evolvable hardware engine can reduce the computing time remarkably (the speedup ratio approximates to 500), and can fully utilize the hardware resources. The systolic technique adopted here also promises to scale up images size with comparatively slower speed of the increasing of the power consumption.