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Erschienen in:
2007 | OriginalPaper | Buchkapitel
Implementing Multi-VRC Cores to Evolve Combinational Logic Circuits in Parallel
verfasst von : Jin Wang, Chang Hao Piao, Chong Ho Lee
Erschienen in: Evolvable Systems: From Biology to Hardware
Verlag: Springer Berlin Heidelberg
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To conquer the scalability issue of evolvable hardware, this paper proposes a multi-virtual reconfigurable circuit (VRC) cores-based evolvable system to evolve combinational logic circuits in parallel. The basic idea behind the proposed scheme is to divide a combinational logic circuit into several sub-circuits, and each of them is evolved independently as a subcomponent by its corresponding VRC core. The virtual reconfigurable circuit architecture is designed for implementing real-world applications of evolvable hardware (EHW) in common FPGAs. In our approach, all the VRC cores are realized in a Xilinx Virtex xcv2000E FPGA as an evolvable system to achieve parallel evolution. The proposed method is evaluated on the evolutions of 3-bit multiplier and adder and compared to direct evolution and incremental evolution in the terms of computational effort and hardware implementation cost.