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Erschienen in:
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2014 | OriginalPaper | Buchkapitel

3. Fast Network-on-Chip Design

verfasst von : Ayan Mandal, Sunil P. Khatri, Rabi N. Mahapatra

Erschienen in: Source-Synchronous Networks-On-Chip

Verlag: Springer New York

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Abstract

In previous Chapter, we showed how resonant clocking can be used as a high-speed, low power, stable, on-chip clock generation and distribution schemes. In this chapter, we use such a clock to design a high speed source-synchronous ring-based NoC architecture. In Sect. 3.1, we introduce our NoC design, which comprises of extremely fast, intersecting source-synchronous data rings. These source-synchronous data rings traverse the CMP in both the horizontal and vertical directions providing complete connectivity to all the PEs in a CMP. In our approach, the interconnection network operates on a different clock domain which runs significantly faster than the PE clocks. This helps us achieve inter-processor communication with minimal latency. We perform architectural simulations of the ring-based NoC in Sect. 3.2. We propose a deadlock-free routing protocol of the source-synchronous ring-based NoC by using link ordering and virtual channel based buffered flow control. Architectural results obtained on synthetic and real traffic demonstrate that the source-synchronous ring-based NoC has significantly lower latency and higher maximum sustained injection rate compared to a state of the art mesh-based NoC. Next, in Sect. 3.3, we propose a modified source-synchronous design in which the PEs extract a low jitter clock directly from the high speed ring clock by division, and hence are synchronous with the NoC. This is feasible due to the extremely good jitter characteristics of the SWO based clock generation and distribution scheme of Sect. 2.2. Using the above modified design, we propose a class of source-synchronous NoCs organized in an H-tree topology which consume lower logic and wiring area compared to a state of the art mesh. Architectural simulations on synthetic and real traffic show that our H-tree based NoC designs can provide significantly lower latency and are able to sustain a higher injection rate compared to a state of the art mesh. Using the modified source-synchronous design proposed in Sect. 3.3, we also evaluate two more floorplan-friendly NoC topologies in Sect. 3.4. These two floorplan-friendly NoC topologies consume significantly lower logic and wiring area compared to a state of the art mesh. Architectural simulations on synthetic and real traffic show that they can provide significantly lower latency while achieving same or better maximum sustained injection rate compared to a state of the art mesh.

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Vorheriges Kapitel Clock Distribution for Fast Networks-on-Chip
Nächstes Kapitel Fast On-Chip Data Transfer Using Sinusoid Signals
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Metadaten
Titel
Fast Network-on-Chip Design
verfasst von
Ayan Mandal
Sunil P. Khatri
Rabi N. Mahapatra
Copyright-Jahr
2014
Verlag
Springer New York
Buch
Source-Synchronous Networks-On-Chip

Print ISBN: 978-1-4614-9404-1

Electronic ISBN: 978-1-4614-9405-8

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-1-4614-9405-8_3

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