nach oben

Erschienen in:

2013 | OriginalPaper | Buchkapitel

7. Fault Tolerant Design and Adaptability

verfasst von : Monica Magalhães Pereira, Eduardo Luis Rhod, Luigi Carro

Erschienen in: Adaptable Embedded Systems

Verlag: Springer New York

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

The continued scaling of current CMOS technology has brought new challenges in device’s fabrication and maintenance. As the feature sizes approach their physical limits, the circuit becomes more prone to faults. For this reason, as the circuits scale to deep-submicron world, including a fault tolerance approach in all devices becomes mandatory. In this chapter, we will show that, besides all the advantages adaptability presents, it can also be a very powerful mechanism to provide fault tolerance to future devices and increase yield and reliability. Chapter5 already discussed some details about using adaptability in Network on Chips targeted to fault tolerance. We continue this discussion by presenting some of the main works on fault tolerance using adaptability, aiming to provide to the reader enough information to understand why and how adaptability is used in this context. This chapter is divided in four primary sections. The first section introduces the reader to fault tolerance and the problems in working with deep-submicron scale. Section7.2 presents the general concepts and terminology used in fault tolerance field and an overview of fault tolerance techniques. Hardware, software, time and information redundancy methods are considered. In Sect.7.3, we discuss some fault tolerance strategies in traditional architectures, multicore systems and reconfigurable architectures. Finally, in Sect.7.4, we present the conclusions on this topic and discuss some open problems.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 340 Zeitschriften

aus folgenden Fachgebieten:

Bauwesen + Immobilien
Business IT + Informatik
Finance + Banking
Management + Führung
Marketing + Vertrieb
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Vorheriges Kapitel Dynamic Optimization Techniques

Nächstes Kapitel Multicore Platforms: Processors, Communication and Memories

Abramovici, M., Stroud, C., Hamilton, C., Wijesuriya, S., Verma, V.: Using roving stars for on-line testing and diagnosis of fpgas in fault-tolerant applications. In: Proceedings of the 1999 IEEE International Test Conference, ITC ’99, p. 973. IEEE Computer Society, Washington, DC (1999). http://dl.acm.org/citation.cfm?id=518925.939331

Abramovici, M., Emmert, J., Stroud, C.: Roving stars: an integrated approach to on-line testing, diagnosis, and fault tolerance for fpgas in adaptive computing systems. In: Proceedings of the Third NASA/DoD Workshop on Evolvable Hardware, 2001, pp. 73–92. IEEE Computer Society, Washington, DC (2001). doi:10.1109/EH.2001.937949

Aggarwal, N., Ranganathan, P., Jouppi, N.P., Smith, J.E.: Configurable isolation: building high availability systems with commodity multi-core processors. In: Proceedings of the 34th Annual International Symposium on Computer Architecture, ISCA ’07, pp. 470–481. ACM, New York (2007). doi:10.1145/1250662.1250720. http://doi.acm.org/10.1145/1250662.1250720

Austin, T.M.: Diva: a reliable substrate for deep submicron microarchitecture design. In: Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, MICRO 32, pp. 196–207. IEEE Computer Society, Washington, DC (1999). http://dl.acm.org/citation.cfm?id=320080.320111

Avizienis, A., Laprie, J.C., Randell, B., Landwehr, C.: Basic concepts and taxonomy of dependable and secure computing. IEEE Trans. Dependable Secur. Comput. 1, 11–33 (2004). doi:10.1109/TDSC.2004.2. http://dx.doi.org/10.1109/TDSC.2004.2

Bernick, D., Bruckert, B., Vigna, P.D., Garcia, D., Jardine, R., Klecka, J., Smullen, J.: Nonstop advanced architecture. In: Proceedings of the 2005 International Conference on Dependable Systems and Networks, DSN ’05, pp. 12–21. IEEE Computer Society, Washington, DC (2005). doi:10.1109/DSN.2005.70. http://dx.doi.org/10.1109/DSN.2005.70

Borkar, S.: Microarchitecture and design challenges for gigascale integration. In: Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, MICRO 37, pp. 3–3. IEEE Computer Society, Washington, DC (2004). doi:10.1109/MICRO.2004.24. http://dx.doi.org/10.1109/MICRO.2004.24

Burger, D.C., Austin, T.M.: The simplescalar tool set, version 2.0. Tech. rep., Technical Report CS-TR-97-1342 – University of Wisconsin (1997)

Center, B.W.R.: Spec announces spec95 benchmark suite as new standard for measuring performance. Tech. rep., Berkley Wireless Research Center (1995)

10.

Corporation, S.P.E.: Spec’s benchmarks and published results. Tech. rep., Standard Performance Evaluation Corporation (2011)

11.

Cuddapah, R., Corba, M.: Reconfigurable logic for fault-tolerance. In: Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications, FPL ’95, pp. 380–388. Springer, London (1995). http://dl.acm.org/citation.cfm?id=647922.741024

12.

DeHon, A., Naeimi, H.: Seven strategies for tolerating highly defective fabrication. IEEE Des. Test 22, 306–315 (2005). doi:10.1109/MDT.2005.94. http://dl.acm.org/citation.cfm?id=1083814.1083884

13.

Dutt, S., Hanchek, F.: Remod: a new methodology for designing fault-tolerant arithmetic circuits. IEEE Trans. Very Large Scale Integr. Syst. 5, 34–56 (1997). doi:10.1109/92.555985. http://dl.acm.org/citation.cfm?id=249537.249548

14.

Dutt, S., Hayes, J.P.: Some practical issues in the design of fault-tolerant multiprocessors. IEEE Trans. Comput. 41, 588–598 (1992). doi:10.1109/12.142685. http://dl.acm.org/citation.cfm?id=146952.146962

15.

Dutt, S., Shanmugavel, V., Trimberger, S.: Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. In: Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD ’99, pp. 173–177. IEEE, Piscataway (1999). http://dl.acm.org/citation.cfm?id=339492.339619

16.

Emmert, J., Bhatia, D.: Incremental routing in fpgas. In: Proceedings of the Eleventh Annual IEEE International ASIC Conference 1998, pp. 217–221 (1998). doi:10.1109/ASIC.1998.722907

17.

Emmert, J.M., Bhatia, D.: Partial reconfiguration of fpga mapped designs with applications to fault tolerance and yield enhancement. In: Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications, pp. 141–150. Springer, London (1997). http://dl.acm.org/citation.cfm?id=647924.738735

18.

Emmert, J.M., Stroud, C.E., Abramovici, M.: Online fault tolerance for fpga logic blocks. IEEE Trans. Very Large Scale Integr. Syst. 15, 216–226 (2007). doi:10.1109/TVLSI.2007.891102. http://dx.doi.org/10.1109/TVLSI.2007.891102

19.

Gold, B.T., Kim, J., Smolens, J.C., Chung, E.S., Liaskovitis, V., Nurvitadhi, E., Falsafi, B., Hoe, J.C., Nowatzyk, A.G.: Truss: A reliable, scalable server architecture. IEEE Micro 25, 51–59 (2005). doi:10.1109/MM.2005.122. http://dl.acm.org/citation.cfm?id=1108266.1108287

20.

Gomaa, M., Scarbrough, C., Vijaykumar, T.N., Pomeranz, I.: Transient-fault recovery for chip multiprocessors. In: Proceedings of the 30th Annual International Symposium on Computer Architecture, ISCA ’03, pp. 98–109. ACM, New York (2003). doi:10.1145/859618.859631. http://doi.acm.org/10.1145/859618.859631

21.

Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: Mibench: A free, commercially representative embedded benchmark suite. In: 2001 IEEE International Workshop on Proceedings of the Workload Characterization, 2001. WWC-4, pp. 3–14. IEEE Computer Society, Washington, DC (2001). doi:10.1109/WWC.2001.15. http://dl.acm.org/citation.cfm?id=1128020.1128563

22.

Hamming, R.W.: Error detecting and error correcting codes. Bell Syst. Tech. J. 29, 147–160 (1950)MathSciNet

23.

Hanchek, F., Dutt, S.: Node-covering based defect and fault tolerance methods for increased yield in fpgas. In: Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication, VLSID ’96, p. 225. IEEE Computer Society, Washington, DC (1996). http://dl.acm.org/citation.cfm?id=525699.834701

24.

Hanchek, F., Dutt, S.: Methodologies for tolerating cell and interconnect faults in fpgas. IEEE Trans. Comput. 47(1), 15–33 (1998). doi:10.1109/12.656073CrossRef

25.

Hatori, F., Sakurai, T., Nogami, K., Sawada, K., Takahashi, M., Ichida, M., Uchida, M., Yoshii, I., Kawahara, Y., Hibi, T., Saeki, Y., Muroga, H., Tanaka, A., Kanzaki, K.: Introducing redundancy in field programmable gate arrays. In: Proceedings of the 1993 IEEE Custom Integrated Circuits Conference, 1993, pp. 7.1.1–7.1.4 (1993). doi:10.1109/CICC.1993.590575

26.

Howard, N., Tyrrell, A., Allinson, N.: The yield enhancement of field-programmable gate arrays. IEEE Trans. Very Large Scale Integr. Syst. 2(1), 115–123 (1994). doi:10.1109/92.273147CrossRef

27.

ITRS: ITRS 2011 Roadmap. Tech. rep., International Technology Roadmap for Semiconductors (2011)

28.

Kastensmidt, F.L., Reis, R., Carro, L.: Fault-Tolerance Techniques for SRAM-Based FPGAs. Springer, Dordrecht (2006)

29.

Kelly, J., Ivey, P.: Defect tolerant sram based fpgas. In: Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1994. ICCD ’94, pp. 479–482 (1994). doi:10.1109/ICCD.1994.331955

30.

Kuo, W., Zuo, M.J.: Optimal Reliability Modeling: Principles and Applications. Wiley, Hoboken (2003)

31.

Lach, J., Mangione-Smith, W.H., Potkonjak, M.: Efficiently supporting fault-tolerance in fpgas. In: Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays, FPGA ’98, pp. 105–115. ACM, New York, NY, USA (1998). DOI 10.1145/275107.275125. URL http://doi.acm.org/10.1145/275107.275125

32.

Lach, J., Mangione-Smith, W.H., Potkonjak, M.: Algorithms for efficient runtime fault recovery on diverse fpga architectures. In: Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems, DFT ’99, pp. 386–394. IEEE Computer Society, Washington, DC (1999). http://dl.acm.org/citation.cfm?id=647832.737827

33.

Lakamraju, V., Tessier, R.: Tolerating operational faults in cluster-based fpgas. In: Proceedings of the 2000 ACM/SIGDA Eighth International Symposium on Field Programmable Gate Arrays, FPGA ’00, pp. 187–194. ACM, New York (2000). doi:10.1145/329166.329205. http://doi.acm.org/10.1145/329166.329205

34.

Mahapatra, N.R., Dutt, S.: Efficient network-flow based techniques for dynamic fault reconfiguration in fpgas. In: Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, FTCS ’99, p. 122. IEEE Computer Society, Washington, DC (1999). http://dl.acm.org/citation.cfm?id=795672.796960

35.

Mitra, S., McCluskey, E.J.: Which concurrent error detection scheme to choose? In: Proceedings of the International Test Conference, pp. 985–994. IEEE Computer Society, Washington, DC (2000). doi:10.1109/TEST.2000.894311

36.

Mukherjee, S.S., Kontz, M., Reinhardt, S.K.: Detailed design and evaluation of redundant multithreading alternatives. In: Proceedings of the 29th Annual International Symposium on Computer Architecture, ISCA ’02, pp. 99–110. IEEE Computer Society, Washington, DC (2002). http://dl.acm.org/citation.cfm?id=545215.545227

37.

Nag, S., Roy, K.: On routability for fpgas under faulty conditions. IEEE Trans. Comput. 44, 1296–1305 (1995). doi:10.1109/12.475125. http://dx.doi.org/10.1109/12.475125

38.

Nakano, J., Montesinos, P., Gharachorloo, K., Torrellas, J.: Revivei/o: efficient handling of i/o in highly-available rollback-recovery servers. In: The Twelfth International Symposium on High-Performance Computer Architecture, 2006, pp. 200–211 (2006). doi:10.1109/HPCA.2006.1598129

39.

Narasimham, J., Nakajima, K., Rim, C., Dahbura, A.: Yield enhancement of programmable asic arrays by reconfiguration of circuit placements. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(8), 976–986 (1994). DOI 10.1109/43.298034CrossRef

40.

Pereira, M., Carro, L.: Dynamically adapted low-energy fault tolerant processors. In: NASA/ESA Conference on Adaptive Hardware and Systems, 2009. AHS 2009, pp. 91–97 (2009). doi:10.1109/AHS.2009.34

41.

Pereira, M.M., Carro, L.: A dynamic reconfiguration approach for accelerating highly defective processors. In: 2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC), pp. 235–238 (2009). doi:10.1109/VLSISOC.2009.6041364

42.

Pereira, M.M., Carro, L.: Dynamic reconfigurable computing: The alternative to homogeneous multicores under massive defect rates. Int. J. Reconfig. Comput. 2011 (2011). doi:10.1155/2011/452589. www.hindawi.com/journals/ijrc/2011/452589/cta/

43.

Pradhan, D.K.: Fault-Tolerant Computer System Design. Prentice Hall, Upper Saddle River (1996)

44.

Quach, N.: High availability and reliability in the itanium processor. IEEE Micro 20, 61–69 (2000). doi:10.1109/40.877951. http://dx.doi.org/10.1109/40.877951

45.

Rabaey, J.M., Chandrakasan, A., Nikolic, B.: Digital Integrated Circuits. Prentice Hall, Upper Saddle River (2003)

46.

Reed, I., Golomb, S.: Polynomial codes over certain finite fields. Jt. Soc. Ind. Appl. Math. J. 8, 300–304 (1960)MATHCrossRef

47.

Romanescu, B.F., Sorin, D.J.: Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, PACT ’08, pp. 43–51. ACM, New York, (2008). doi:10.1145/1454115.1454124. http://doi.acm.org/10.1145/1454115.1454124

48.

Rotenberg, E.: Ar-smt: A microarchitectural approach to fault tolerance in microprocessors. In: Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing, FTCS ’99, p. 84. IEEE Computer Society, Washington, DC (1999). http://dl.acm.org/citation.cfm?id=795672.796966

49.

Rotenberg, E., Jacobson, Q., Sazeides, Y., Smith, J.: Trace processors. In: Proceedings of the 30th Annual ACM/IEEE International Symposium on Microarchitecture, MICRO 30, pp. 138–148. IEEE Computer Society, Washington, DC (1997). http://dl.acm.org/citation.cfm?id=266800.266814

50.

Sorin, D.J., Martin, M.M.K., Hill, M.D., Wood, D.A.: Safetynet: improving the availability of shared memory multiprocessors with global checkpoint/recovery. In: Proceedings of the 29th Annual International Symposium on Computer Architecture, ISCA ’02, pp. 123–134. IEEE Computer Society, Washington, DC (2002). http://dl.acm.org/citation.cfm?id=545215.545229

51.

Srinivasan, J., Adve, S.V., Bose, P., Rivers, J.A.: Lifetime reliability: Toward an architectural solution. IEEE Micro 25, 70–80 (2005). DOI 10.1109/MM.2005.54. URL http://dl.acm.org/citation.cfm?id=1079834.1079936

52.

Stott, E., Sedcole, P., Cheung, P.: Fault tolerance and reliability in field-programmable gate arrays. IET Comput. Digit. Tech 4(3), 196–210 (2010). doi:10.1049/iet-cdt.2009.0011CrossRef

53.

Sundaramoorthy, K., Purser, Z., Rotenburg, E.: Slipstream processors: improving both performance and fault tolerance. In: Proceedings of the ninth international conference on Architectural support for programming languages and operating systems, ASPLOS-IX, pp. 257–268. ACM, New York, NY, USA (2000). DOI 10.1145/378993.379247. URL http://doi.acm.org/10.1145/378993.379247

54.

Tsu, W., Macy, K., Joshi, A., Huang, R., Walker, N., Tung, T., Rowhani, O., George, V., Wawrzynek, J., DeHon, A.: Hsra: high-speed, hierarchical synchronous reconfigurable array. In: Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field programmable Gate Arrays, FPGA ’99, pp. 125–134. ACM, New York (1999). doi:10.1145/296399.296442. http://doi.acm.org/10.1145/296399.296442

55.

Tullsen, D., Eggers, S., Levy, H.: Simultaneous multithreading: Maximizing on-chip parallelism. In: Proceedings of the 22nd Annual International Symposium on Computer Architecture, 1995, pp. 392–403. ACM, New York (1995)

56.

Weaver, C., Austin, T.M.: A fault tolerant approach to microprocessor design. In: Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS), DSN ’01, pp. 411–420. IEEE Computer Society, Washington, DC (2001). http://dl.acm.org/citation.cfm?id=647882.738066

57.

Webber, S., Beirne, J.: The stratus architecture. In: Fault-Tolerant Computing, 1991. FTCS-21. Digest of Papers., Twenty-First International Symposium, pp. 79–85 (1991). doi:10.1109/FTCS.1991.146637

58.

White, M., Chen, Y.: Scaled cmos technology reliability users guide. Tech. rep., Jet Propulsion Laboratory, National Aeronautics and Space Administration (2008)

59.

Zhou, H.: Dual-core execution: Building a highly scalable single-thread instruction window. In: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques, PACT ’05, pp. 231–242. IEEE Computer Society, Washington, DC (2005). doi:10.1109/PACT.2005.18. http://dx.doi.org/10.1109/PACT.2005.18

Titel: Fault Tolerant Design and Adaptability
verfasst von: Monica Magalhães Pereira
Eduardo Luis Rhod
Luigi Carro
Verlag: Springer New York
Buch: Adaptable Embedded Systems
Print ISBN: 978-1-4614-1745-3

Electronic ISBN: 978-1-4614-1746-0

Copyright-Jahr: 2013
DOI: https://doi.org/10.1007/978-1-4614-1746-0_7

Neuer Inhalt

Bildnachweise

VDI-Icon, Profil Icon, inhalt2, Springer Professional Modul/© Springer Fachmedien Wiesbaden GmbH, Zukunftswerkstatt Sales Excellence_ieS/© Springer Fachmedien Wiesbaden GmbH, Search Icon, Banner Hanser, Dr. Alexandru Oproiescu/© Dr. Alexandru Oproiescu, Julian Erhard/© Packex GmbH, Cloud Netzwerk Open Banking/© vege / Fotolia, Zeitschrift Wissensmanagement Cover, PatentFit-Logo/© Springer Fachmedien Wiesbaden GmbH, Zukunftswerkstatt Sales Excellence 2024/© AndreyPopov / Getty Images / iStock, 2023_Antrieb/© supervisuell, ATZ-Webinar: Prototypenfreie Entwicklung durch Offline- und Driver-in-the-Loop-HiL-Tests /© (c) VI-grade

Springer Professional

Abstract

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Springer Professional "Wirtschaft"

Neuer Inhalt

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.