5. Finite State Machines

This chapter deals with the implementation of Finite State Machines (FSM) in VHDL for the modeling and design of sequential digital circuits. State machines can be classified into two types: Moore and Mealy. The state transition diagram is an efficient design tool that can be used to describe finite state machines represented as a set of transitions, which may or may not be labeled. The main design guidelines for FSM as well as the importance of multi-process FSM will be discussed in this chapter. Additionally, this chapter illustrates practical examples of FSMs such as the 4-bit BCD counter, sequence detector and parity checker that are useful in actual practice. Finally, test and validation of these practical examples have been done on the FPGA platform.