Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes

In computer science, there is a growing gap between what technology can do and our ability to design such systems. This is known as the design gap. Systems-on-chips (SoCs) pack in numerous components, from CPUs and GPUs to accelerators and wireless functions, making them more intricate than entire 1990s desktop computers. Manufacturing and understanding these integrated circuits is impossible without electronic design automation (EDA) tools.

The traditional sequential design phases—specification, HW design, and software design—lead to time inefficiencies and the risk of project failures due to wrong design decisions. Virtual prototyping, by allowing simultaneous software and hardware development, addresses these challenges, reducing development time by half. However, the combination of software and hardware in embedded systems demands not only verified functionality but also increased security.

While virtual prototyping has gained popularity, modeling and verification processes still are mostly manual efforts. The need for stable, open source RISC-V VPs is emphasized to accelerate innovation and improve product quality. The challenges include the long development time, inefficient design space exploration, inadequate re-use of intermediate models, lack of early system analysis tools, and a high verification hurdle.

This section gives an overview over the common topics the following chapters build upon to keep this book self-contained. Individual, per-chapter specific topics (such as security lattices, Section 4.3) will however be introduced in their respective subsections. As the proposed advanced design flow is focused on embedded devices (ranging from simple microcontrollers to huge SoCs), the concept of embedded devices and how they are usually laid out is explained first. The development of such devices is nowadays aided with VPs, so the status quo of virtual prototyping with a focus on modeling with SystemC and TLM in particular is explained, and the trade-off between simulation accuracy and execution speed is introduced. Lastly, a summary and the rationale of the RISC-V ISA and its ecosystem, which is used as a functional case-study in this book, are outlined.

This chapter explores the role of RISC-V in the Internet of Things (IoT) era, emphasizing its popularity due to its open and free instruction set architecture. The chapter introduces virtual prototypes (VPs) as a crucial tool, addressing the gap between early system design and fully finished systems. It presents a RISC-V based VP that supports multi-core platforms, operating systems, and offers faster simulation compared to RTL. The discussion extends to an Environment Model GUI for simulation of off-chip devices, and a debugging visualization tool called RISCVIEW, and a method to bridge the TLM/RTL gap in SoC design using Hardware-in-the-Loop (HWITL) simulations with FPGAs. The proposed VPIL strategy enables early Design Space Exploration (DSE) and validation, enhancing the efficiency of SoC development. The chapter concludes with suggestions for further extensions to the approach for specialized applications.

This chapter emphasizes the critical need for thorough verification of embedded systems, building upon the advantages of SystemC models outlined in the previous chapter. SystemC models, being modular and offering multiple abstraction layers, serve as ideal early evaluation and reference models for hardware/software co-design. As SystemC Virtual Prototypes (VPs) are internally C/C\(++\) models, the proposed approaches take advantage from the well-established set of tools in computer science. Two main verification categories, hardware-centric and software-centric, are discussed, utilizing simulation-based and formal techniques. The industry emphasizes early hardware model verification to detect specification, design, and implementation flaws promptly. The chapter introduces novel verification approaches for real-world SystemC TLM peripherals using symbolic execution tools, cross-level verification of actual RTL models against TLM counterparts, and a pioneering method for early and accurate Dynamic Information Flow Tracking (DIFT) of binaries targeting embedded systems with custom peripherals. The effectiveness is demonstrated through extensive experiments, including security policy violation detection and analysis of an AES encryption peripheral.

The conclusion underscores the escalating impact of digital systems on security and safety, emphasizing the imperative to enhance the quality of embedded systems and ICs. The book introduces an efficient design process utilizing architecture-level VPs, presenting novel approaches for rapid design space exploration and advanced verification techniques. The contributions are categorized into Modeling and Verification fields. Modeling innovations include a high-performance RISC-V VP, a virtual Environment Model GUI for off-chip devices, introspection improvements through RISCVIEW, and closing the TLM/RTL gap with VPITL. In the Verification domain, unique methods for early HW TLM model verification, cross-level verification of RTL/TLM peripheral models, and DIFT-based security policy evaluation are presented. These contributions enhance the reliability and repeatability of complex systems, promoting a systematic and trustworthy approach to complex system design. Finally, future studies are suggested for further improvements in various stages of the design process.