nach oben

Erschienen in:

2024 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Pascal Pieper, Rolf Drechsler

Erschienen in: Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes

Verlag: Springer Nature Switzerland

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

In computer science, there is a growing gap between what technology can do and our ability to design such systems. This is known as the design gap. Systems-on-chips (SoCs) pack in numerous components, from CPUs and GPUs to accelerators and wireless functions, making them more intricate than entire 1990s desktop computers. Manufacturing and understanding these integrated circuits is impossible without electronic design automation (EDA) tools.

The traditional sequential design phases—specification, HW design, and software design—lead to time inefficiencies and the risk of project failures due to wrong design decisions. Virtual prototyping, by allowing simultaneous software and hardware development, addresses these challenges, reducing development time by half. However, the combination of software and hardware in embedded systems demands not only verified functionality but also increased security.

While virtual prototyping has gained popularity, modeling and verification processes still are mostly manual efforts. The need for stable, open source RISC-V VPs is emphasized to accelerate innovation and improve product quality. The challenges include the long development time, inefficient design space exploration, inadequate re-use of intermediate models, lack of early system analysis tools, and a high verification hurdle.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Nächstes Kapitel Preliminaries

CISC/RISC: Complex/Reduced Instruction Set Computer. See also Sect. 2.3 and [12].

MIPS: Microprocessor without Interlocked Pipelined Stages.

B. Menhorn, F. Slomka, Confirming the design gap, in Advances in Computational Science, Engineering and Information Technology, ed. by D. Nagamalai, A. Kumar, A. Annamalai (Springer International Publishing, Heidelberg, 2013), pp. 281–292. ISBN: 978-3-319-00951-3CrossRef

Semiconductor Industry Association. 2008 International Technology Roadmap for Semiconductors (ITRS) (2008) [Online]. Available: https://cseweb.ucsd.edu/classes/wi09/cse242a/itrs/ORTC.pdf (visited on 2022-11)

J. Henkel, Embedded computing - closing the SoC design gap. Computer 36(9), 119–121 (2003). https://doi.org/10.1109/mc.2003.1231200.CrossRef

1666-2011 - IEEE Standard for Standard Systemc Language Reference Manual (IEEE, Piscataway, 2012), pp. 1–638. https://doi.org/10.1109/IEEESTD.2012.6134619

OSCI TLM-2.0 Language Reference Manual OSCI (2009)

E. Sotiriou-Xanthopoulos, S. Xydis, K. Siozios, G. Economakos, D. Soudris, Rapid prototyping and design space exploration methodologies for many-accelerator systems, in 2015 25th International Conference on Field Programmable Logic and Applications (FPL) (2015), pp. 1–2. https://doi.org/10.1109/FPL.2015.7293990

D. Große, R. Drechsler, System-Level Verification (Springer Netherlands, Dordrecht, 2010). ISBN: 978-90-481-3631-5. https://doi.org/10.1007/978-90-481-3631-5_3 [Online]

R. Leupers et al., Virtual platforms: breaking new grounds, in 2012 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2012), pp. 685–690. https://doi.org/10.1109/DATE.2012.6176558

O. Hagenbruch, Taschenbuch Mikroprozessortechnik (Hanser Verlag, Munich, 2004). ISBN: 978-3446220720

10.

F. Vahid, What is hardware/software partitioning? SIGDA Newsl. 39(6), 1 (2009). ISSN: 0163-5743. https://doi.org/10.1145/1862900.1862901 [Online]

11.

Mirabilis Design Inc. Hardware-software partitioning in system-on-chip (SoC) (2022) [Online]. Available https://www.mirabilisdesign.com/hardware-software-partitioning-in-system-on-chip-soc/ (visited on 2022-11)

12.

E. Blem, J. Menon, K. Sankaralingam, Power struggles: revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures, in 2013 IEEE 19th International Symposium on High Performance Computer Architecture (HPCA) (2013), pp. 1–12. https://doi.org/10.1109/HPCA.2013.6522302

13.

S.B. Furber, ARM System-on-Chip Architecture (Pearson Education, London, 2000). ISBN: 978-0201675191.

14.

U. Degenbaev, Formal Specification of the x86 Instruction Set Architecture, Formelle spezifizierung von dem x86-befehlssatz (2012). https://doi.org/10.22028/D291-26338

15.

C. Domas, Breaking the x86 ISA, Black Hat, 2017 [Online]. Available: https://www.blackhat.com/docs/us-17/thursday/us-17-Doma-sBreaking-The-x86-ISA.pdf

16.

A. Waterman, K. Asanović, The RISC-V Instruction Set Manual; Volume I: User-Level ISA (RISC-V Foundation, Berkeley, 2019). https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-118.pdf; https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf

17.

A. Waterman, K. Asanović, The RISC-V Instruction Set Manual; Volume II: Privileged Architecture (RISC-V Foundation, Berkeley, 2019). https://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-161.pdf

18.

RISC-V calling convention (2018) [Online]. Available: https://riscv.org/wp-content/uploads/2015/01/riscv-calling.pdf (visited on2018-05)

19.

Alibaba cloud unveils chip development platform to support developers with RISC-V based high-performance SoCs. (2022) [Online]. Available: https://www.alibabacloud.com/de/press-room/alibaba-unveils-risc-v-chip-development-platform (visited on 2022-08)

20.

Die RISC-V-basierten SSD-controller kommen (2020) [Online]. Available: https://www.golem.de/news/seagate-und-western-digital-die-risc-v-basierten-ssd-controller-kommen-2012-152690.html (visited on 2022-08)

21.

R. Leupers et al., Virtual platforms: Breaking new grounds, in 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE) (2012), pp. 685–690. https://doi.org/10.1109/DATE.2012.6176558

22.

L. Bossuet, G. Gogniat, Chapter 5: hardware security in embedded systems. Communicating Embedded Syst. 2010-01. https://doi.org/10.1002/9781118557624.ch5

23.

D. Papp, Z. Ma, L. Buttyan, Embedded systems security: threats, vulnerabilities, and attack taxonomy, in 2015 13th Annual Conference on Privacy, Security and Trust (PST) (2015), pp. 145–152. https://doi.org/10.1109/PST.2015.7232966

24.

HiPEAC. New startup machineware enables ultra-fast RISC-V simulation (2022) [Online]. Available: https://www.hipeac.net/news/6996/new-startup-machineware-enables-ultra-fast-risc-v-simulation/ (visited on 2022-11)

25.

J. Vanwell, 10 IoT security incidents that make you feel less secure (2021) [Online]. Available: https://conosco.com/industry-insights/blog/iot-security-breaches-4-real-world-examples (visited on 2022-11)

26.

CisoMag Authors, 10 IoT security incidents that make you feel less secure (2020) [Online]. Available: https://embeddedartistry.com/fieldatlas/historical-software-accidents-and-errors/ (visited on 2022-11)

27.

Semiconductor Industry Association, 2015 International Technology Roadmap for Semiconductors (ITRS) (2015) [Online]. Available: https://www.semiconductors.org/wp-content/uploads/2018/06/02015-ITRS-2.0-Executive-Report-1.pdf (visited on 2022-11)

28.

Y. Xu et al., Processors using agile methodology, in 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO) (2022), pp. 1178–1199

29.

S.D. Anthony, 3 ways to fail cheap (2009) [Online]. Available: https://hbr.org/2009/03/why-focusing-on-innovation-suc (visited on 2022-11)

30.

V. Herdt, R. Drechsler, Advanced virtual prototyping for cyber-physical systems using RISC-V: implementation, verification and challenges. Sci. China Inform. Sci. 65 (2022). https://doi.org/10.1007/s11432-020-3308-4.

31.

N. Bruns, V. Herdt, D. Große, R. Drechsler, Efficient cross-level processor verification using coverage-guided fuzzing, in Proceedings of the Great Lakes Symposium on VLSI 2022, ser. GLSVLSI ’22, Irvine (Association for Computing Machinery, New York, 2022), pp. 97–103. ISBN: 9781450393225 [Online]. Available: https://doi.org/10.1145/3526241.3530340

32.

S. Tempel, V. Herdt, R. Drechsler, An effective methodology for integrating concolic testing with systemc-based virtual prototypes, in 2021 Design, Automation and Test in Europe Conference and Exhibition (DATE) (2021), pp. 218–221. https://doi.org/10.23919/DATE51398.2021.9474149

33.

S. Tempel, V. Herdt, R. Drechsler, SISL: concolic testing of structured binary input formats via partial specification, in Automated Technology for Verification and Analysis, ed. by A. Bouajjani, L. Holík, Z. Wu (Springer International Publishing, Cham, 2022), pp. 77–82. ISBN: 978-3-031-19992-9CrossRef

34.

J. Zielasko, S. Tempel, V. Herdt, R. Drechsler, 3D visualization of symbolic execution traces, in Forum on Specification and Design Languages (2022), pp. 1–8. https://doi.org/10.1109/FDL56239.2022.9925664

35.

V. Herdt, D. Große, S. Tempel, R. Drechsler, Adaptive simulation with virtual prototypes in an open-source RISC-V evaluation platform. J. Syst. Archit. 116, 102135 (2021). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2021.102135 [Online]. Available: https://www.sciencedirect.com/science/article/pii/S1383762121001016

36.

V. Herdt, D. Große, J. Wloka, T. Güneysu, R. Drechsler, Verification of embedded binaries using coverage-guided fuzzing with systemc-based virtual prototypes, in Proceedings of the 2020 on Great Lakes Symposium on VLSI, ser. GLSVLSI’20, Virtual Event (Association for Computing Machinery, New York, 2020), pp. 101–106. ISBN: 9781450379441 [Online]. Available: https://doi.org/10.1145/3386263.3406899

37.

N. Bruns, V. Herdt, R. Drechsler, Unified HW/SW coverage: a novel metric to boost coverage-guided fuzzing for virtual prototype based HW/SW co-verification, in Forum on Specification and Design Languages, FDL 2022, Linz, September 14–16, 2022 (IEEE, Piscataway, 2022), pp. 1–8 [Online]. Available: https://doi.org/10.1109/FDL56239.2022.9925661

38.

V. Herdt, D. Große, P. Pieper, R. Drechsler, RISC-V based virtual prototype: an extensible and configurable platform for the system-level. J. Syst. Archit. 109, 101756 (2020). ISSN: 1383-7621. https://doi.org/10.1016/j.sysarc.2020.101756CrossRef

39.

P. Pieper, V. Herdt, R. Drechsler, Advanced environment modeling and interaction in an open source RISC-V virtual prototype, in Proceedings of the Great Lakes Symposium on VLSI 2022, ser. GLSVLSI ’22, Irvine (Association for Computing Machinery, New York, 2022), pp. 193–197. ISBN: 9781450393225. https://doi.org/10.1145/3526241.3530374

40.

P. Pieper, V. Herdt, R. Drechsler, Advanced embedded system modeling and simulation in an open source RISC-V virtual prototype. J. Low Power Electron. Appl. 12(4) (2022). ISSN: 2079-9268. https://doi.org/10.3390/jlpea12040052 [Online]. Available: https://www.mdpi.com/2079-9268/12/4/52

41.

F. Böseler, J. Walter, B.R. Perjikolaei, A comparison of Virtual Platform Simulation Solutions for timing prediction of small RISC-V based SoCs, in Forum on Specification and Design Languages (2022), pp. 1–8. https://doi.org/10.1109/FDL56239.2022.9925667

42.

M. Koenig, R. Rasch, Digital teaching an embedded systems course by using simulators, in 2021 ACM/IEEE Workshop on Computer Architecture Education (WCAE) (2021), pp. 1–7. https://doi.org/10.1109/WCAE53984.2021.9707146

43.

Renode, (2022) [Online]. Available: https://renode.io/ (visited on2022-04)

44.

P. Pieper, R. Wimmer, G. Angst, R. Drechsler, Minimally invasive HW/SW co-debug live visualization on architecture level, in Proceedings of the 2021 on Great Lakes Symposium on VLSI, ser. GLSVLSI ’21, Virtual Event (Association for Computing Machinery, New York, 2021), pp. 321–326. ISBN: 9781450383936. https://doi.org/10.1145/3453688.3461524

45.

P. Pieper, V. Herdt, D. Große, R. Drechsler, Dynamic information flow tracking for embedded binaries using SystemC-based virtual prototypes, in 2020 57th ACM/IEEE Design Automation Conference (DAC) (2020), pp. 1–6. https://doi.org/10.1109/DAC18072.2020.9218494

46.

P. Pieper, V. Herdt, R. Drechsler, Verifying SystemC TLM peripherals using modern C++ symbolic execution tools, in 2022 59th ACM/IEEE Design Automation Conference (DAC) (2022), pp. 1–6. https://doi.org/10.1145/3489517.3530604

47.

P. Pieper, Symbolic SystemC kernel framework (2022) [Online]. Available: https://github.com/agra-uni-bremen/symsysc (visited on 2022-12-20)

48.

P. Pieper, Virtual breadboard GUI (2022) [Online]. Available: https://github.com/agra-uni-bremen/virtual-breadboard (visited on 2022-12-20)

49.

P. Pieper, V. Herdt, S. Tempel, K.A. Rudkowski, S. Ahmadi-Pour, N. Bruns, RISC-V virtual prototype (2021) [Online]. Available: https://github.com/agra-uni-bremen/riscv-vp (visited on 2022-12-20)

50.

P. Pieper, Dynamic information flow analysis with the RISC-V VP (2022) [Online]. Available: https://github.com/agra-uni-bremen/riscvdfa (visited on 2022-12-20)

51.

P. Pieper, Virtual peripheral in-the-loop: protocol (2023) [Online]. Available: https://github.com/agra-uni-bremen/virtual-bus (visited on 2023-03-24)

52.

S. Ahmadi-Pour, P. Pieper, R. Drechsler, Virtual-peripheral-in-the-loop: a hardware-in-the-loop strategy to bridge the VP/RTL design-gap (2023). arXiv:2311.00442 [cs.AR]

Titel: Introduction
verfasst von: Pascal Pieper
Rolf Drechsler
Verlag: Springer Nature Switzerland
Buch: Formal and Practical Techniques for the Complex System Design Process using Virtual Prototypes
Print ISBN: 978-3-031-51691-7

Electronic ISBN: 978-3-031-51692-4

Copyright-Jahr: 2024
DOI: https://doi.org/10.1007/978-3-031-51692-4_1

Neuer Inhalt

Bildnachweise

VDI-Icon, Profil Icon, inhalt2, Springer Professional Modul/© Springer Fachmedien Wiesbaden GmbH, Die Gewinner und Laudatoren des Sustainability Award in Automotive 2024/© Uli Regenscheit | ATZlive, Search Icon, Banner Hanser, Additiv gefertigte Teile/© Marina_Skoropadskaya | Getty Images | iStock, Warnschild "Land unter"/© Bluedesign / Fotolia, Gardiner von Trapp/© Alpega Group, Zeitschrift Wissensmanagement Cover, PatentFit-Logo/© Springer Fachmedien Wiesbaden GmbH, ATZ-Webinar: Prototypenfreie Entwicklung durch Offline- und Driver-in-the-Loop-HiL-Tests /© (c) VI-grade, chassis.tech plus 2023/© [M] ATZlive / TÜV SÜD PRODUCT SERVICE GMBH, adäsion-Webinar-Matinee/© krystiannawrocki_ Getty Images

Springer Professional

Abstract

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Neuer Inhalt

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.