Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Bücher
Zeitschriften
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
SLX-Digitalkonferenz: Zukunftswerkstatt 2024

Mehr Umsatz mit Top-Kontakten

Am 7. Mai erfahren Sie, wie Vertriebsteams Leadgenerierung, Leadnurturing und Leadstrategien effizient steuern können.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Patent Issues of Fan-Out Wafer-Level Packaging Kapitel lesen Erstes Kapitel lesen

2018 | OriginalPaper | Buchkapitel

5. FOWLP: Chip-First and Die Face-Down

verfasst von : John H. Lau

Erschienen in: Fan-Out Wafer-Level Packaging

Verlag: Springer Singapore

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The first fan-out wafer-level packaging (FOWLP) U.S. patent was filed by Infineon on October 31, 2001 (Hedler et al. in Transfer Wafer Level Packaging, 2001 [1]; Lau in Chip Scale Rev. 19:42–46, 2015 [2]), and the first technical papers were also published (at ECTC2006 and EPTC2006) by Infineon and their industry partners: Nagase, Nitto Denko, and Yamada (Brunnbauer et al. in IEEE/ECTC Proceedings, 547–551, 2006 [3]; Brunnbauer et al. in IEEE/EPTC Proceedings, 1–5, 2006 [4]). At that time, they called it embedded wafer-level ball (eWLB) grid array.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Embedded Chip Packaging
Nächstes Kapitel FOWLP: Chip-First and Die Face-Up
Literatur
1.
Hedler, H., T. Meyer, and B. Vasquez. 2001. Transfer Wafer Level Packaging. U.S. Patent 6 727 576 B2, April 27, 2001.
2.
Lau, J.H. 2015. Patent Issues of Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 19: 42–46.
3.
Brunnbauer, M., E. Furgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, E. Nomura, K. Kiuchi, and K. Kobayashi. 2006. An Embedded Device Technology Based on a Molded Reconfigured Wafer. In IEEE/ECTC Proceedings, May 2006, 547–551.
4.
Brunnbauer, M., E. Furgut, G. Beer, and T. Meyer. 2006. Embedded Wafer Level Ball Grid Array (eWLB). In IEEE/EPTC Proceedings, December 2006, 1–5.
5.
Keser, B., C. Amrine, T. Duong, O. Fay, S. Hayes, G. Leal, W. Lytle, D. Mitchell, and R. Wenzel. 2007. The Redistributed Chip Package: A Breakthrough for Advanced Packaging. In Proceedings of IEEE/ECTC, 2007, 286–291.
6.
Kripesh, V., V. Rao, A. Kumar, G. Sharma, K. Houe, X. Zhang, K. Mong, N. Khan, and J. H. Lau. 2008. Design and Development of a Multi-Die Embedded Micro Wafer Level Package. In IEEE/ECTC Proceedings, 2008, 1544–1549.
7.
Khong, C., A. Kumar, X. Zhang, S. Gaurav, S. Vempati, V. Kripesh, J.H. Lau, and D. Kwong. 2009. A Novel Method to Predict Die Shift During Compression Molding in Embedded Wafer Level Package. In IEEE/ECTC Proceedings, 2009, 535–541.
8.
Sharma, G., S. Vempati, A. Kumar, N. Su, Y. Lim, K. Houe, S. Lim, V. Sekhar, R. Rajoo, V. Kripesh, and J.H. Lau. 2009. Embedded Wafer Level Packages with Laterally Placed and Vertically Stacked Thin Dies. In IEEE/ECTC Proceedings, 2009, 1537–1543. Also, IEEE Transactions on CPMT 1 (5): 52–59 (May 2011).
9.
Kumar, A., D. Xia, V. Sekhar, S. Lim, C. Keng, S. Gaurav, S. Vempati, V. Kripesh, J.H. Lau, and D. Kwong. 2009. Wafer Level Embedding Technology for 3D Wafer Level Embedded Package. In IEEE/ECTC Proceedings, 2009, 1289–1296.
10.
Lim, Y., S. Vempati, N. Su, X. Xiao, J. Zhou, A. Kumar, P. Thaw, S. Gaurav, T. Lim, S. Liu, V. Kripesh, and J. H. Lau. Demonstration of High Quality and Low Loss Millimeter Wave Passives on Embedded Wafer Level Packaging Platform (EMWLP). In IEEE/ECTC Proceedings, 2009, 508–515. Also, IEEE Transactions on Advanced Packaging 33: 1061–1071 (2010).
11.
Lau, J.H., N. Fan, and M. Li. 2016. Design, Material, Process, and Equipment of Embedded Fan-Out Wafer/Panel-Level Packaging. Chip Scale Review 20 (May/June):38–44.
12.
Kurita, Y., T. Kimura, K. Shibuya, H. Kobayashi, F. Kawashiro, N. Motohashi, and M. Kawano. 2010. Fan-Out Wafer-Level Packaging with Highly Flexible Design Capabilities. In IEEE/ESTC Proceedings, 2010, 1–6.
13.
Motohashi, N., T. Kimura, K. Mineo, Y. Yamada, T. Nishiyama, K. Shibuya, H. Kobayashi, Y. Kurita, and M. Kawano. 2011. System in Wafer-Level Package Technology with RDL-First Process. In IEEE/ECTC Proceedings, 2011, 59–64.
14.
Yoon, S., J. Caparas, Y. Lin, and P. Marimuthu. 2012. Advanced Low Profile PoP Solution with Embedded Wafer Level PoP (eWLB-PoP) Technology. In IEEE/ECTC Proceedings, 2012, 1250–1254.
15.
Tseng, C., C. Liu, C. Wu, and D. Yu. 2016. InFO (Wafer Level Integrated Fan-Out) Technology. In IEEE/ECTC Proceedings, 2016, 1–6.
16.
Hsieh, C., C. Wu, and D. Yu. 2016. Analysis and Comparison of Thermal Performance of Advanced Packaging Technologies for State-of-the-Art Mobile Applications. In IEEE/ECTC Proceedings, 2016, 1430–1438.
17.
Lau, J.H. 2016. TSV-less Interposers. Chip Scale Review 20 (September/October):28–35.
18.
Yoon, S., P. Tang, R. Emigh, Y. Lin, P. Marimuthu, and R. Pendse. 2013. Fanout Flipchip eWLB (Embedded Wafer Level Ball Grid Array) Technology as 2.5D Packaging Solutions. In IEEE/ECTC Proceedings, 2013, 1855–1860.
19.
Lin, Y., W. Lai, C. Kao, J. Lou, P. Yang, C. Wang, and C. Hseih. 2016. Wafer Warpage Experiments and Simulation for Fan-out Chip on Substrate. In IEEE/ECTC Proceedings, 2016, 13–18.
20.
Chen, N., T. Hsieh, J. Jinn, P. Chang, F. Huang, J. Xiao, A. Chou, and B. Lin. 2016. A Novel System in Package with Fan-Out WLP for High Speed SERDES Application. In IEEE/ECTC Proceedings, 2016, 1495–1501.
21.
Hayashi, N., T. Takahashi, N. Shintani, T. Kondo, H. Marutani, Y. Takehara, K. Higaki, O. Yamagata, Y. Yamaji, Y. Katsumata, and Y. Hiruta. 2011. A Novel Wafer Level Fan-out Package (WFOPTM) Applicable to 50 µm Pad Pitch Interconnects. In IEEE/EPTC Proceeding, December 2011, 730–733.
22.
Hayashi, N., H. Machida, N. Shintani, N. Masuda, K. Hashimoto, A. Furuno, K. Yoshimitsu, Y. Kikuchi, M. Ooida, A. Katsumata, and Y. Hiruta. 2014. A New Embedded Structure Package for Next Generation, WFOPTM (Wide Strip Fan-Out Package). In Pan Pacific Symposium Conference Proceedings, February 2014, 1–7.
23.
Hayashi, N., M. Nakashima, H. Demachi, S. Nakamura, T. Chikai, Y. Imaizumi, Y. Ikemoto, F. Taniguchi, M. Ooida, and A. Yoshida. 2017. Advanced Embedded Packaging for Power Devices. In IEEE/ECTC Proceedings, 2017, 696–703.
24.
Braun, T., K.-F. Becker, S. Voges, T. Thomas, R. Kahle, J. Bauer, R. Aschenbrenner, and K.-D. Lang. 2013. From Wafer Level to Panel Level Mold Embedding. In IEEE/ECTC Proceedings, 2013, 1235–1242.
25.
Braun, T., K.-F. Becker, S. Voges, J. Bauer, R. Kahle, V. Bader, T. Thomas, R. Aschenbrenner, and K.-D. Lang. 2014. 24 × 18 Fan-Out Panel Level Packing. In IEEE/ECTC Proceedings, 2014, 940–946.
26.
Braun, T., S. Raatz, S. Voges, R. Kahle, V. Bader, J. Bauer, K. Becker, T. Thomas, R. Aschenbrenner, and K. Lang. 2015. Large Area Compression Molding for Fan-Out Panel Level Packing. In IEEE/ECTC Proceedings, 2015, 1077–1083.
27.
Chang, H., D. Chang, K. Liu, H. Hsu, R. Tai, H. Hunag, Y. Lai, C. Lu, C. Lin, and S. Chu. 2014. Development and Characterization of New Generation Panel Fan-Out (PFO) Packaging Technology. In IEEE/ECTC Proceedings, 2014, 947–951.
28.
Liu, H., Y. Liu, J. Ji, J. Liao, A. Chen, Y. Chen, N. Kao, and Y. Lai. 2014. Warpage Characterization of Panel Fab-out (P-FO) Package. In IEEE/ECTC Proceedings, 2014, 1750–1754.
29.
Lau, J.H., M. Li, M. Li, T. Chen, I. Xu, X. Qing, et al. 2018. Fan-Out Wafer-Level Packaging for Heterogeneous Integration. In IEEE/ECTC Proceedings, May 2018.
30.
Lau, J.H., M. Li, N. Fan, E. Kuah, Z. Li, K. Tan, T. Chen, et al. 2017. Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution-Layers (RDLs). IMAPS Transactions on Journal of Microelectronics and Electronic Packaging, 123–131.
Metadaten
Titel
FOWLP: Chip-First and Die Face-Down
verfasst von
John H. Lau
Copyright-Jahr
2018
Verlag
Springer Singapore
Buch
Fan-Out Wafer-Level Packaging

Print ISBN: 978-981-10-8883-4

Electronic ISBN: 978-981-10-8884-1

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-981-10-8884-1_5

Neuer Inhalt

    Bildnachweise