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Erschienen in:
2007 | OriginalPaper | Buchkapitel
FPGA Accelerator For Medical Image Compression System
verfasst von : Prof. K. A. Mohamed Junaid, Dr. G. Ravindrann
Erschienen in: 3rd Kuala Lumpur International Conference on Biomedical Engineering 2006
Verlag: Springer Berlin Heidelberg
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This Project describes the benefits of using an FPGA as a Co-processor for Digital Signal Processor, for increasing speed and reducing the power consumption. This approach uses the advantage of fine grain parallel operation of FPGA. An ASIC implementation of a filter algorithm might have numerous MACs so that, all the taps can be processed in parallel. Likewise, FPGA has a flexible architecture that can be used for all MAC operations in parallel. Programmable logic combines the flexibility of a general-purpose DSP and ASIC. In this project the Spartan 2E FPGA has been interfaced with TMS320C6711 DS Processor. The speed is improved 453.52 times than the conventional DSP processor implementation.