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Erschienen in:
2010 | OriginalPaper | Buchkapitel
FPGA Implementation of AES Co-processor in Counter Mode
verfasst von : Balwinder Singh, Harpreet Kaur, Himanshu Monga
Erschienen in: Information Processing and Management
Verlag: Springer Berlin Heidelberg
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In many applications strong security and high speed performance is required. For this purpose, DES and AES techniques are usually chosen, but these results in the lowering of security strength and less throughput. This paper presents the design FPGA implementation of AES processor in Counter Mode for 256 bits. In this work, the encryption rate is 52.6124 G bits /sec and memory efficiency is 1.565 with the key length of 256 bits. HDL simulations, verifications and implementations are done on Spartran 3, vertex 2 and vertex E devices.