Handbook of Memristor Networks

This tutorial clarifies the axiomatic definition of $$(v^{(\alpha )},i^{(\beta )})$$ circuit elements via a look-up-table dubbed an A-pad,A-pad of admissible (v, i) signals measured via Gedanken Probing Circuits. The $$(v^{(\alpha )},i^{(\beta )})$$ elements are ordered via a complexity metric. Under this metric, the memristor emerges naturally as the fourth element Tour (Nature 453:42–43, 2008 [1]), characterized by a state-dependent Ohm’s law. A logical generalization to memristive devices reveals a common fingerprint consisting of a dense continuum of pinched hysteresis loops whose area decreases with the frequency $$\omega $$ and tends to a straight line as $$\omega \rightarrow \infty $$, for all bipolar periodic signals and for all initial conditions. This common fingerprint suggests that the term memristor be used henceforth as a moniker for memristive devices.

This paper presents an in-depth review of the memristor from a rigorous circuit-theoretic perspective, independent of the material the device is made of. From an experimental perspective, a memristor is best defined as any 2-terminal device that exhibits a pinched hysteresis loopHysteresis loop in the voltage-current plane when driven by any periodic voltage or current signal that elicits a periodic response of the same frequency. This definition greatly broadens the scope of memristive devices to encompass even non-semiconductor devices, both organic and inorganic, from many unrelated disciplines, including biology, botany, brain science, etc. For pedagogical reasons, the broad terrain of memristors is partitioned into 3 classes of increasing generality, dubbed Ideal Memristors, Generic Memristors, and Extended Memristors. Each class is distinguished from the others via unique fingerprintsFingerprint and signatures. This paper clarifies many confusing issues, such as non-volatilityNon-volatility , DC V-I curvesV–I curve , high-frequency v-i curves, local activity, as well as nonlinear dynamical and bifurcation phenomena that are the hallmarks of memristive devices. Above all, this paper addresses several fundamental issues and questions that many memristor researchers do not comprehend but are afraid to ask.

This paper classifies all memristors into three classes called Ideal, Generic, or Extended memristors. A subclass of Generic memristors is related to Ideal memristors via a one-to-one mathematical transformation, and is hence called Ideal Generic memristors. The concept of non-volatile memories is defined and clarified with illustrations. Several fundamental new concepts, including Continuum-memory memristor, POP (acronym for Power-Off Plot), DC V-I Plot, and Quasi DC V-I Plot, are rigorously defined and clarified with colorful illustrations. Among many colorful pictures the shoelace DC V-I Plot stands out as both stunning and illustrative. Even more impressive is that this bizarre shoelace plot has an exact analytical representation via 2 explicit functions of the state variable, derived by a novel parametric approach invented by the author.

In this chapter, a personal guide to the set of Leon Chua’s papers that I have found most helpful in my research will be provided in the hope that this will encourage others to study them and answer the questions they have. Then, the chapter will be finished with some observations and comments about Prof. Leon Chua’s definition of memristor in mathematics.

This chapter illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: (1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic and not symmetrical. (2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and (3) the pinched hysteresis loopHysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In additionAddition , two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.

All 2-terminal non-volatile memory devices based on resistance switching Resistance switching are memristors, regardless of the device material and physical operating mechanisms. They all exhibit a distinctive “fingerprint” characterized by a pinched hysteresis loop confined to the first and the third quadrants of the v-i plane whose contour shape in general changes with both the amplitude and frequency of any periodic “sine-wave-like” input voltage source, or current source. In particular, the pinched hysteresis loop shrinks and tends to a straight line as frequency increases. Though numerous examples of voltage versus current pinched hysteresis loops have been published in many unrelated fields, such as biology, chemistry, physics, etc., and observed from many unrelated phenomena, such as gas discharge arcs, mercury lamps, power conversion devices, earthquake conductance variations, etc., we restrict our examples in this tutorial to solid state and/or nano devices where copious examples of published pinched hysteresis loops abound. In particular, we sampled arbitrarily, one example from each year between the years 2000 and 2010, to demonstrate that the memristor is a device that does not depend on any particular material, or physical mechanism. For example, we have shown that spin-transfer magnetic tunnel junctions are examples of memristors. We have also demonstrated that both bipolar and unipolar resistance switching devices are memristors. The goal of this tutorial is to introduce some fundamental circuit-theoretic concepts and properties of the memristor that are relevant to the analysis and design of non-volatile nano memories where binary bits are stored as resistances manifested by the memristor’s continuum of equilibrium states. Simple pedagogical examples will be used to illustrate, clarify, and demystify various misconceptions among the uninitiated.

The recent discovery of memristor has sparked renewed interest in the scientific community about state dependent resistances. In the current paper, we show that the detector used in the first radios, called cats whisker, had memristive properties. We have identified the state variable governing the resistance state of the device and can program it to switch between multiple stable resistance states. Our observations are valid for a larger class of devices called coherers, including cats whisker. We further argue that these constitute the missing canonical physical implementations for a memristor.

This paper clarifies why the “memristor” is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memristor”. It is shown that the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory but the memistor is an ad hoc 3-terminal devise for one specific application. The memistor is difficult to predict its behavior when it is connected with other circuit elements.

This chapter is updated from an earlier version [63]. In the few years since that book chapter was written, there have been several thousand papers published on the topic of memristors, but very few new compact memristor modelsMemristor model have appeared. This is not a reflection of the maturity of the field but rather the difficulty of constructing an accurate and predictive compact mathematical model for an electronic circuit element that displays memristor behavior. Given the rapid advances in the field in general, it is time to provide another snapshot of the state of memristor modeling, even though any such attempt will be incomplete. Such models are essential for designing and simulating complex integrated circuits that contain memristors, and the types of applications being considered are increasing significantly. Although the fundamental equations that specify the device physics may be known, they usually comprise a set of coupled nonlinear integro-differential equations that are extremely challenging to solve in three dimensions, and standard multi-physics solvers may not have all the components needed for an accurate model. A numerical solution of the physics equations can require supercomputers and long execution times, which makes this approach useless for interactive simulation of large circuits that contain many such elements. Thus, the equations must be simplified dramatically, and it is not always clear which terms are the most important for the behavior of the device. On the other hand, a purely black box approach of fitting a set of experimental measurements to a convenient functional form runs the risk of poorly representing the behavior of the device in operating regimes outside the range in which the data were collected. Thus, a hybrid approach is necessary, in which the mathematical formalism for a memristor provides the framework for the model and knowledge of the device physics defines the state variable(s), operating limits and asymptotic behavior necessary to make the model useful. After describing the challenge, the art and science of constructing a memristor modelMemristor model are illustrated by three examples: a completely rewritten description of a locally active and volatile device based on a thin film of niobium dioxide that undergoes both a thermal instability and an insulator to metal transition because of Joule heating, the original description of a nonvolatile memory device based on titanium dioxideTitanium dioxide in which the effective width of an electron tunnel barrier is determined by oxygen vacancy drift caused by an applied electric field, and the recent detailed examination of the transport properties and identification of the primary state variable for tantalum oxide.

From a pedagogical point of view, the memristor is defined in this tutorial as any 2-terminal device obeying a state-dependent Ohm’s law. This tutorial also shows that from an experimental point of view, the memristor can be defined as any 2-terminal device that exhibits the fingerprints of “pinched” hysteresis loops in the v-i plane. It also shows that memristors endowed with a continuum of equilibrium states can be used as non-volatile analog memories. This tutorial shows that memristors span a much broader vista of complex phenomena and potential applications in many fields, including neurobiology. In particular, this tutorial presents toy memristors that can mimic the classic habituation and LTP learning phenomena. It also shows that sodium and potassium ion-channel memristors are the key to generating the action potential in the Hodgkin-Huxley equations, and that they are the key to resolving several unresolved anomalies associated with the Hodgkin-Huxley equations. This tutorial ends with an amazing new result derived from the new principle of local activity, which uncovers a minuscule life-enabling Goldilocks zone, dubbed the edge of chaos, where complex phenomena, including creativity and intelligence, may emerge. From an information processing perspective, this tutorial shows that synapses are locally-passive memristors, and that neurons are made of locally-active memristors.

This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axonsNeuron axon of our neuronsNeuron are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figuresLissajous figure in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover, the pinched hysteresis loops for the potassiumIon potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel memristors are destined to be classic examples of locally-activeNeuron action potential memristorsMemristor neuron in future textbooks on circuit theory and bio-physics.

The memristor, the fourth fundamental electric element, was conceptually proposed by L. Chua in 1971 and was found in laboratory late in 2008. Recently a special type of memristor was considered to be able to mimic the behavior of neural synapses. In particular, attributed to the long-term memory of weight changes, the memristor can reproduce the spike-timing-dependent plasticity (STDP) protocol of a synapse, displaying a synaptic modification related to the time interval of pre- and post-synaptic spikes. Not limited to it, we found that the memristor with adaptive thresholds can even mimic higher-order behavior of synapses, realizing the well-known suppression principle of Froemke. This type of memristor can actually express both long-term and short-term plasticities in synapses, which are responsible for the excitation level and the refractory time, respectively. The corresponding dynamical process is governed by a set of ordinary differential equations. Interestingly, the Froemke’s model and our memristor-like model, based on two completely different mechanisms, are found to be quantitatively equivalent. In this chapter we would like to provide this new perspective of looking at synaptic dynamics.

Memristors are an important emerging technology for memory and neuromorphic computing applications. In this chapter, we review the fundamentals of the memistor framework developed by Leon Chuan nearly 40 years ago, and examine resistive switching phenomena as the quintessential example of physical memristive systems. A special focus is given to the hardware emulation of biological synapses using memristors and groundbreaking results in the field are reviewed. Future research directions with spiking neural networks is outlined and the exciting prospect of emergent behavior in memristor networks is discussed.

The self-organization of dynamical structures in complex natural systems is associated with an intrinsic capacity for computation. Beginning from the context of modern trends in neuromorphic engineering, this work introduces an effort toward the construction of purpose-built dynamical systems. Known as Atomic switch networksatomic switch networks (ASN), these systems consist of highly interconnected, physicallyRecurrent networks recurrent networks of inorganic synapses (atomic switches). By combining the advantages of controlled design with those of self-organization, the functional topology of ASNs has been shown to produce emergent system-wide dynamics and a diverse set of complex behaviors with striking similarity to those observed in many natural systems including biological neural networks and assemblies. Numerical modeling and experimental investigations of their operational characteristics and intrinsic dynamical properties have facilitated progress toward toward implementation in neuromorphic reservoir computing.Reservoir computing These achievements demonstrate the utility of ASNs as a uniquely scalable physical platform capable of exploring the dynamical interface of complexity, neuroscience, and engineering.

Here we present a very exciting overlap between emergent nano technology and neuroscience, which has been discovered by neuromorphic engineers. Specifically, we are linking one type of memristor nano technology devices to the biological synaptic update rule known as Spike-Time-Dependent-Plasticity found in real biological synapses. Understanding this link allows neuromorphic engineers to develop circuit architectures that use this type of memristors to artificially emulate parts of the visual cortex. We focus on the type of memristors referred to as voltage or flux driven memristors and focus our discussions on behavioral macro models for such devices. The implementations result in fully asynchronous architectures with neurons sending their action potentials not only forwards but also backwards. One critical aspect is to use neurons that generate spikes of specific shapes. We will see how by changing the shapes of the neuron action potential spikes we can tune and manipulate the STDP learning rules for both excitatory and inhibitory synapses. We will see how neurons and memristors can be interconnected to achieve large scale spiking learning systems, that follow a type of multiplicative STDP learning rule. We will briefly extend the architectures to use three-terminal transistors with similar memristive behavior. We will illustrate how a V1 visual cortex layer can be assembled and how it is capable of learning to extract orientations from visual data coming from a real artificial CMOS spiking retina observing real life scenes. Finally, we will discuss limitations of currently available memristors. The results presented are based on behavioral simulations and do not take into account non-idealities of devices and interconnects. The aim here is to present, in a tutorial manner, an initial framework for the possible development of fully asynchronous STDP learning neuromorphic architectures exploiting two or three terminal memristive type devices.

Neuromorphic computing systems are under heavy investigation as a potential substitute for the traditional von Neumann systems in high-speed low-power applications. One way to implement neuromorphic systems in hardware is to use the new emerging devices such as Resistive RAM (ReRAM or Memristor), because of the promising features these devices provide, such as low feature size, extremely low power consumption, synaptic like behavior, and scalability. However, these systems are in their early developing stages and still have many challenges to be solved before they can be mature enough for commercialization. In this work, we are going to investigate hardware implementation of neuromorphic systems. Specifically, this work will study hardware implementation for two types of neural networks; feed forward neuromorphic systems and Echo State Network (ESN) model, as a special type of Recurrent Neural Networks (RNNs). In addition, detailed design procedure for designing and simulating the proposed architecture, along with a detailed system evaluation will be provided.

Memristive devices, such as resistive switching memory (RRAM) and phase change memory (PCM), show variable resistance which can mimic the synaptic plasticity in the human brain. This fascinating analogy has provided the inspiration for many recent research advances, involving memristive devices and their use as artificial electronics synapses in neuromorphic circuits with learning capability. In particular, RRAM-based artificial synapses are extremely promising in terms of area efficiency, low power consumption, and flexibility of design which pave the way for spiking neural networks that perform and behave like the human brain. This chapter will review the state of the art about the design and development of memristive neural networks for unsupervised learning. First, the optimization of RRAM devices for synaptic applications will be discussed, and a novel RRAM device with improved resistance window and controllability of resistance will be introduced. Then, a hybrid CMOS/memristive synaptic circuit will be shown to carry out learning tasks via the spike-timing dependent plasticity (STDP), which is one of the learning rules in biological synapses. Finally, the neural networks based on RRAM synapses will be reviewed, covering both feed-forward networks and recurrent networks. In both cases, the network displays unsupervised learning of input patterns, which can be stored, recognized, or even reconstructed by the network, thus highlighting the wealth of potential promising applications for memristive networks with synaptic plasticity.

Bio-inspired neuromorphic computing has drawn increasing attention due to its potential for massively parallel, energy efficient and fault tolerantFault tolerance computation, e.g. nonstructured data processing, where memristors are considered as promising building blocks for the construction of neuromorphic networks. However, the lack of clear understanding on memristive switching dynamics (especially for oxide memristors), the undesirable nonlinearity in conductanceConductance modulation, and the inherent variations in present devices have hampered the implementation of neuromorphic device and functional networksNetworks . Here this chapter presents an approach to directly resolving ion transport dynamics in oxide based memristors via electrostatic force microscopy (EFM). Utilizing this method, unambiguous evidence of oxygen ion migration, accumulation, and conduction channel formation in HfO2 has been clearly observed, providing insights into the microscopic operation principles of oxide based memristors. These understandings are subsequently used to develop novel approaches to engineering the analog switching linearity and the number of weight states in memristive synapses. Moreover, both planar and vertical multi-terminal memristive devices capable of implementing heterosynaptic plasticity are demonstrated, enriching the functionality of memristive components. After incorporation into crossbar networks, the heterosynaptic plasticity endows the devices with facilely tunable learning rate that is highly desirable for achieving optimized learning scheme with accelerated learning and high accuracy at the same time. Finally, a fuzzy restricted Boltzmann machine (FRBM) network is proposed to tolerate device variation that is intrinsic to memristors based on ionic transport mechanism, thus paving the way for highly robust neuromorphic computingMemristor neuromorphic computing based on memristors.

Binary state resistance switching memristors and multistate or continuum resistance memristors have begun to diverge in their application. The former application in non-volatile logic memory and the later with more focus on neuromorphic computation. The properties of continuum resistance memristors as neuromorphic hardware are presented in this paper. Concepts such as polymorphism, voltage fluxFlux equivalence and non voltage based memristive flux are discussed. Emergent functionalities observed in neuromorphic hardware such as associative enhancement of current/chargeCharge generation, spike time dependent plasticitySpike time dependent plasticity short-term plasticity (STDP) Learning log-STDP and associative memory between voltage and light pulse stimuli are expanded upon. Finally various applications that this hardware may enable such as machine learning and adaptive programs for brain-like functionality are discussed.

Bio-inspired computational systems must be based on elements involved, similarly to the brain, in both memorizing and processing of the information. This paper is dedicated to organic memristive devices—elements that were designed and constructed for mimicking the most important properties of synapses, responsible for Hebbian type of learning. We will consider the architecture of the device and its properties, as well as circuits and networks with adaptive features.

We describe a biological network and the principal mechanisms that are responsible for learning and memory. We start with a description of the morphology of these networks and their components, such as neurons and synapses. Then, we will identify crucial components of the information processing, such as ion flux and the induced mechanisms, e.g., long-term potentiation and depression. Next, we will compare the behaviour of a memristive system with the mechanisms identified in biological systems and present corresponding experiments and a few simulations. Finally, we will present more abstract ways of using memristors to solve complex problems.

A novel memristor bridge circuit which is able to perform zero, negative and positive synaptic weightings in neuron cells is proposed. It is composed of four memristors and three transistors for weighting operation and voltage-to-current conversion, respectively. It is compact as it can be fabricated in nano meter scale. It is power efficient since its operation is pulse-based. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. By programming on each memristor of the memristor bridge circuit, the signed weighting values can be set on the memristor bridge synapses. The features of proposed architecture are investigated via various simulations.

Cellular Nonlinear/Nanoscale Networks (CNNs) that can provide parallel processing in massive scale is known suitable to neuromorphic applications such as vision systems. In CNN, synaptic weights can be calculated by digital or analog multiplication. Though the conventional CMOS digital circuits can be used in calculating this multiplication for CNN applications, they occupy very large area and need large power consumption, especially when many multiplications should be calculated in parallel in massive scale. On the other hand, analog circuits seem very attractive in calculating multiplication of CNN applications. Here input signal current is multiplied by memristance that can be programmed. In this chapter, we introduce some analog circuits for CNN applications that use memristance in calculating multiplication. In addition, we discuss memristor models and some practical problems in CNN circuits that should be resolved in real implementation of CNN circuits.

Of the many network representations in which memristors can be modelled, neural networks are perhaps the most enticing as they open the possibility for neuromorphic computing—biologically-inspired brainlike information processing in hardware. Memristors are analogous to biological synapses; both feature nonvolatile resistance, a charge-dependent plastic response to activity, and can provide adaptive learning when coupled with a Hebbian mechanism. In this chapter, various types of memristors are deployed as synapses in spiking networks. Biological information processing implies autonomous learning control—a neuro-evolutionary approach provides this functionality and is used to search for beneficial network topologies. The main focus of this work extends the remit of the evolutionary algorithm to alter the conductance profiles of individual memristors, creating networks of heterogeneous variable synapses. These variable memristor networks are tested against networks of benchmark synapses in a robotic pathfinding scenario. Experimental findings conclude that the variable synapses bestow more behavioural degrees of freedom to the networks, allowing them to outperform the comparative synapse types.

Neuromorphic computation using Spiking Neural Networks (SNN) Spiking Neural Networks (SNN) is proposed as an alternative solution for future of computation to conquer the memory bottelneck issue in recent computer architecture. Different spike codings have been discussed to improve data transferring and data processing in neuro-inspired computation paradigms. Choosing the appropriate neural network topology could result in better performance of computation, recognition and classification. The model of the neuron is another important factor to design and implement SNN systems. The speed of simulation and implementation, ability of integration to the other elements of the network, and suitability for scalable networks are the factors to select a neuron model. The learning algorithms are significant consideration to train the neural network for weight modification. Improving learning in neuromorphic architecture is feasible by improving the quality of artificial synapse as well as learning algorithm such as STDP. In this chapter we proposed a new synapse box that can remember and forget. Furthermore, as the most frequent used unsupervised method for network training in SNN is STDP, we analyze and review the various methods of STDP. The sequential order of pre- or postsynaptic spikes occurring across a synapse in an interval of time leads to defining different STDP methods. Based on the importance of stability as well as Hebbian competition or anti-Hebbian competition the method will be used in weight modification. We survey the most significant projects that cause making neuromorphic platform. The advantages and disadvantages of each neuromorphic platform are introduced in this chapter.

The present high demand for data classification in novel computing paradigms originated a huge growth in the machine learning field. The next step consists in the hardware implementation of the idealized artificial neural networks, for which memristors grant a low power and scalable solution. The conductance of a memristor (memristance) offers the possibility of working both in binary (0 or 1) or continuous ([0, 1]) states. In the first case, it can represent the nodes in an associative neural network (e.g. a Willshaw networkWillshaw network), while in the later it can represent the trainable weights in a classifying perceptron algorithm. This chapter reviews the theoretical basics and algorithm implementation of Willshaw and single-layer perceptron memristor-based networks. The two algorithms, developed using the open-source python language, are made available to the public for particular testing, implementation and further development.

Memristors have been suggested for the use as artificial synapses and have performed well in this role in simulations with artificial spiking neurons. We will show that real world memristors natively spike and describe the properties of these spikes. A network of purely memristors should not show any behaviour in addition to that expected from a single memristor. Networks of 2 and 3 memristor combinations were investigated. We demonstrate that, if the memristors are wired together with opposing polarity, oscillations and bursting spikes emerge. We compare two types of memristors, ‘filamentary’ and standard memristors (which are closer to Chua’s theoretical memristors), and found that standard memristors do not exhibit these rich behaviours if they are wired with the same polarity. We propose that these oscillations and spikes may be similar phenomenon to brainwaves and neural spike trains and suggest that these behaviours can be used to perform brain-like computation.

Memristors are promising building blocks for next-generation non-volatile memory, bio-inspired computing, and beyond. Currently, however, they are still suffering from several difficulties that prevent their mass production, including material compatibility and large array operation. In this chapter, we first survey research efforts on using silicon oxide as the switching material, and various ways to integrate selectors with silicon oxide based memristors for large array operation. A self-rectifying unipolar p-Si/SiO2/n-Si memristor is then introduced. The resistive switching is related to the formation and the rupture of a highly localized Si-rich conduction channel, as suggested by both electrical characterization and direct observation using transmission electron microscope (TEM). The self-rectifying behavior is attributed to a p-i-n diode at each junction at low resistance state, and negates the need for an external selector in a passive memristor array. Finally, we discuss three-dimensional crossbars of all-Si based memristors. The effectiveness of the built-in diodes in blocking both intra- and inter-layer sneak pathSneak path current is confirmed with both simulation and experiments.

The basic self-directed channel memristor is comprised of five layers of Ge2Se3, SnSe, and an oxidizable metal, Ag. Each layer plays a role in the operation of the memristor, influencing both the electrical and thermal properties of the device. Device operation can be altered by manipulation of these layers through material changes, layer ordering, or layer exclusion. In this chapter the function of the SnSe layer is explored through electrical characterization of several device types in which this metal chalcogenideChalcogenide layer has been altered, either by changing the metal, or replacing Se with Te.

Resistive switchingAntiparallel resistive switches devices or memristors are an emerging and greatly potential technology for future information technology, such as internet of things (IoT) and artificial intelligence (AI)Artificial intelligence (AI) . In this chapter, we firstly review the resistive switching mechanismsResistive switching materials , since its complex nature involving electronic and ionic kinetics serves as the basics for the applications on device and system levels. Secondly, the performance improvement methods from aspects of material, device and programming are summarized. Finally, we will present the integration technology and point out issues that should be addressed in 2D and 3D architectures.

Memristor is a new circuit element defined by a state-dependent Ohm’s law between the memristor voltage and current. It has recently been successfully built, however, its electrical characteristics are not fully known yet. Like other circuit elements R, L and C, there could have various configurations of multiple memristors including serial and parallel connections in a variety of applications. When input voltage/current is supplied to a circuit with multiple memristors, behavior of the device becomes complicated and is difficult to predict. In this chapter, composite characteristics of the serial and parallel connections of memristors are investigated using both linear and nonlinear models. Also, the behavior of individual memristor is formulated mathematically and a general computation method of composite memristance for multiple memristor circuits of diverse configurations is proposed.

This chapter proposes and studies a memristor-based chaotic system, which is constructed by incorporating a memristor into the canonical Chen oscillator with boundary conditions. Specifically, charge-controlled and flux-controlled memristor models with appropriate boundary conditions are introduced and the relation between the charge through and the flux across the memristor is derived. The rich and interesting dynamical behaviors of the memristive system are demonstrated. In particular, chaosChaos in the system is verified by conventional means of, for instance, the Lyapunov exponentLyapunov exponent spectrum, observation of chaotic attractors,Chaotic attractor as well as basic bifurcation analysis.Bifurcation analysis Finally, a basic analog circuit implementation of the memristive chaotic system based on PSPICE is presented.

One-dimensional (1D) memristive networks are the simplest type of memristive networks one can imagine. Yet, despite their morphological simplicity, such networks represent an important class of memory networks characterized by the strongest interaction among the network components. This chapter reviews several important dynamical features of 1D memristive networks composed of realistic threshold-type memristive systems. First of all, the accelerated and decelerated switching regimes of memristive systems are introduced and exemplified. Secondly, the phenomenon of switching synchronization is presented. Finally, it is shown that metastable transmission lines composed of metastable memristive circuits can be used to transfer the information from one space location to another. Here, the information transfer occurs in the form of a switching front propagating along the line resembling a kink in, say, classical $$\phi ^4$$ field theory model. Importantly, such memristive kinks can also be used for information processing purposes. This chapter thus reveals the triad of memristive systems functionalities in their 1D networks: information processing, storage and transfer.

Almost 50 years have been completed ever since Leon ChuaMemristor proposed the existence of a new class of passive circuit elements, which he called memristors and memristive devices. Nowadays, the unique electrical characteristics associated with them, concerning nanoscale dimensions, nonvolatility, and CMOS BEOL integration compatibility, along with the advantages of crossbar structures, have the potential to revolutionize computing architectures. Being associated with the totally nonlinear behavior of individual memristive elements, circuits of multiple memristors may work in very complicated way, quite difficult to predict, due to the polarity–dependent nonlinear variation in the memory resistance (memristance) of individual memristors. A well defined and effective memristor model for circuit design combined with a design paradigm which exploits the composite memristance of the resistive switching elements, based on well understood underlying logic design principles, would certainly accelerate research on new computing schemes using nanoscale circuits and systemsMemristormodel. Towards this goal, we explore the dynamics of regular networkMemristornetworks geometries containing only memristive devices and present a memristor crossbar circuit design paradigm in which memristors are modeled using the quantum mechanical phenomenon of tunneling. We use this circuit model to test various logic circuit designs capable of universal computation. Finally, we develop and present a novel CMOS-like design paradigm for memristor–based crossbar circuitsMemristorcircuit.

The missing link between a nonlinear circuit element that is able to self-adjust its conductance according to the history of applied voltage/current and physical realizations of two-terminal oxide-based resistive memory was discovered in early 2008, and has since then been intensively studied. This class of memory devices is called memristive devicesMemristivedevice, which includes resistive random access memories (RRAM)Memristivedeviceresistive random access memory, phase change memories (PCM)Memristivedevicephase change memory and spin-transfer torque magnetoresistive memories (STT-MRAM)Memristive devicespin-transfer torque magnetoresistive memory. Memristive devices are mostly CMOS and fab friendly, and promise simpler architecture, high scalability and stackability (3D), good selectivity, relatively, low-power consumption, high endurance and retention, and fast operation by utilizing parallelism, and the most important of all, the ability to merge logic and memory. A significantly wide range of material systems show that resistive switchingResistive switching can be categorized under three main redox-related effects, electrochemical metalization effects (ECM)Resistive switchingelectrochemical metalization effect, valency change memory effect (VCM)Resistive switchingvalency change memory effect and thermochemical memory effects (TCM)Resistive switchingthermochemical memory effect. Although, the behavior of these resistive memories can be modeled using high-level finite-state machines (FSMs), the underlying switching mechanisms is yet to be fully understood. Despite this shortage, their application in memory and computing has been constantly improved. These devices can be programmed to exhibit multi-level cell (MLC) and binary cell behavior, thus analog and digital memories can be exists in one device depends on programming. In this chapter, we highlight some of the in situIn-situ computing computational capability of memristive devices.

We give a general overview on Silicon nanowire-based multi-terminal memristive devices. The functionality of the devices can be used for logic, memory and sensing applications. It is shown that three- and four- terminal memristive devices can be used for both logic and memory applications. In particular, Schottky-barrier silicon nanowire FETs are very interesting devices due to their CMOS-compatibility and ease of fabrication.

Memristive logic design, the methodology of designing logic circuits using memristors, is an emerging concept whose growth is fueled by the quest for energy-efficient computing systems. Many memristive logic families have evolved, with diverse attributes, and a mature comparison is needed to judge their merits. This chapter presents a framework for comparing logic families by classifying them on the basis of fundamental properties, statefulness, proximity (to the memory array), and flexibility of computation. We propose metrics to compare memristive logic families using analytic expressions for latency, energy efficiency, and area. We then conduct a case study of an eight-bit addition operation to demonstrate our evaluation methodology. We also perform vector operations and give insights into the potential of these logic families to compute on large sets of data. Our purpose is to provide a methodology for comparing existing logic families and facilitate the evaluation of new ones.

Memristive stateful logic refers to a form of computational logic in which memristors both store logic values and perform logical operations on these values. We present a generalized form of memristive stateful logic and define the logic operations realizable in this form. We also consider the CMOS circuitry required for reliable implementation of memristive stateful logic. Furthermore, synthesis of arbitrary Boolean functions and the parallelization of stateful logic to memristive crossbars is presented.

This chapter describes strategies for performing basic additionAddition and multiplicationMultiplication in memristor-based structures. An overview of both analog and digital approaches for addition and multiplication is presented. Examples of memristor-based designs of ripple carry addersRipple carry adder and array multipliersArray multiplier are shown.

There are three possible stages of exploring the memristor as the fourth fundamental circuit elementFundamental circuit element via its model: (1) Generation of the model, (2) Simulation of the element behavior with the aid of the model, and (3) Hardware emulationHardware emulators of the memristorEmulation of memristor . This chapter deals with the third stage, describing circuit ideas of memristor emulatorsMemristor emulator for practical laboratory experiments.

Global optimisation problems in networks often require shortest path length computations to determine the most efficient route. The simplest and most common problem with a shortest path solution is perhaps that of a traditional labyrinth or maze with a single entrance and exit. Many techniques and algorithms have been derived to solve mazes, which often tend to be computationally demanding, especially as the size of maze and number of paths increase. In addition, they are not suitable for performing multiple shortest path computations in mazes with multiple entrance and exit points. Mazes have been proposed to be solved using memristive networks and in this paper we extend the idea to show how networks of memristive elements can be utilised to solve multiple shortest paths in a single network. We also show simulations using memristive circuit elements that demonstrate shortest path computations in both 2D and 3D networks, which could have potential applications in various fields.

In this paper, we first present a biorealistic model for the first part of early vision processing by incorporating memristive nanodevices. The architecture of the proposed network is based on the organisation and functioning of the Outer Plexiform Layer (OPL) and Inner Plexiform Layer (IPL) in the vertebrate retina. The non-linear and adaptive response of memristive devices make them excellent building blocks for realizing complex synaptic- like architectures that are common in the human retina. We particularly show how that hexagonal memristive grids can be employed for faithfully emulating the smoothing effect occuring in the OPL to enhance the dynamic range of the system. A memristor-based thresholding scheme is employed for detecting the edges of grayscale images, while evaluating the proposed system’s adaptability to different lighting conditions and fault tolerance capacity. We then extend our work to computing relative motion of objects, which is an important navigation task that vertebrates routinely perform by relying on inherently unreliable biological cells in the retina. Here, a novel memristive thresholding scheme that facilitates the detection of moving edges is introduced. In addition, a double-layered 3-D memristive network is employed for modeling the motion computations that take place in both the OPL and IPL that enables the detection of on-center and off-center transient responses. Applying the transient detection results, it is shown that it is possible to generate an estimation of the speed and direction a moving object.

This chapter introduces the concept of a memcapacitor, and reviews different approaches to its physical realization. Also, practical constraints for their usage are assessed. Because of their compatibility with traditional circuit integration technologies, two approaches are particularly interesting: the ferroelectric capacitor and the memcapacitor constructed by appending metal-insulator-metal (MIM) capacitor with a memristive switching layer. Ferroelectric capacitors have already been in use for many years so the properties of this technology are relatively well researched. The MIM-memristor hybrid structure can take advantage of the vital research on memristive memories. With sufficiently large ratio of the OFF and ON resistances of a memristive material, the compound structure behaves as a memcapacitive system. Finally, the potential of memcapacitors for memory and logic applications as well as for artificial neural networks are discussed.

This chapter presents dynamic behaviors of a new reaction-diffusion-type excitable medium, where the diffusion coefficient is represented by memristive dynamics. The medium consists of an array of excitable Oregonators, and each Oregonator is locally coupled with other Oregonators via memristors, which were claimed to be the fourth circuit element exhibiting a relationship between flux $$\phi $$ and charge q. By using the medium, this chapter exhibits that (i) the memristor conductances are modulated by the excitable waves and controlled the velocity of the waves, depending on the memristor’s polarity, and (ii) nonuniform spatial patterns are generated depending on the initial condition of Oregonator’s state, memristor polarity and stimulation.

Physarum polycephalum’s foraging has been for a long time a real source of inspiration for scientists and researchers as it exhibits intrinsic optimization characteristics. When some sources of nutrients are present, Physarum connects these sources with its protoplasmic vascular network, along shortest path connections. This chapter presents the modeling of Physarum’s learning and adaptivity to periodic environmental changes by a memristor-based passive LC filter, and further demonstrates its computational capabilities through two different electronic approaches. Firstly, a circuit-level model of Physarum’s oscillatory internal motion mechanism is designed to emulate the local signal propagation and the expansion of its vascular network during biological shortest path finding experiments. Furthermore, an extension of this model in a system-level approach is presented, which introduces also the shrinking mechanism that Physarum performs to reduce its power consumption after it has reached every nutrient source within its environment. The proper functioning of both the aforementioned approaches was verified via circuit simulations in SPICE as well as MATLAB. Finally, the effect of environmental noise was integrated to the presented approaches, permitting their evaluation under more realistic circumstances closer to the biological experiments, with very interesting results.

In this Chapter, a Cellular Neural/Nonlinear Network (CNN) made of memristor-based cells is introduced. The Memristive CNN consists of identical cells, each containing a memristor, an inductor and a capacitor. We show how the Memristive CNN is able to generate autowaves. We investigate then an FPGA-based implementation of it and related experimental results confirming the capabilities of the system to generate autowaves. This shows that memristor can be used not only as a fundamental block of new chaotic circuits, but also to build complex systems made of interacting memristor-based elementary cells. In such systems many complex phenomena may take place like the autowave propagation discussed in this Chapter and thus feasible hardware emulators allowing an experimental investigation of systems based on electrical analogues of memristor devices are required. In this Chapter such a platform has been realized by using an FPGA-based approach which also has the further advantage of being flexible and easily adaptable to the study of other memristor-based complex systems.

In this paper, we design a cellular automaton and a discrete-time cellular neural network (DTCNN) using nonlinear passive memristors. They can perform a number of applications, such as logical operations, image processing operations, complex behaviors, higher brain functions, etc. By modifying the characteristics of nonlinear memristors, the memristor DTCNN can perform almost all functions of memristor cellular automaton. Furthermore, it can perform more than one function at the same time, that is, it allows multitasking.