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Erschienen in: Design Automation for Embedded Systems 2/2013

01.06.2013

Instruction scheduling with k-successor tree for clustered VLIW processors

verfasst von: Xuemeng Zhang, Hui Wu, Jingling Xue

Erschienen in: Design Automation for Embedded Systems | Ausgabe 2/2013

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Abstract

Clustering is a well-known technique for improving the scalability of classical VLIW (Very Long Instruction Word) processors. A clustered VLIW processor consists of multiple clusters. Each cluster has a local register file and a set of functional units. This paper proposes a novel phase coupled, priority-based heuristic for scheduling a set of operations in a basic block on a clustered VLIW processor. Our heuristic converts the instruction scheduling problem to the problem of scheduling a set of operations with a common deadline. The priority of each operation v i is the l max (v i )-successor-tree-consistent deadline. This deadline is the upper bound on the latest completion time of v i in any feasible schedule for a relaxed problem where the precedence-latency constraints only between v i and all its successors are considered. We have simulated our heuristic and the Integrated heuristic on the 808 basic blocks taken from the MediaBench II benchmark suite using three processor models. On average, for the three processor models, our heuristic improves over the Integrated heuristic by 13 %, 18 %, 16 %, respectively.

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Fußnoten
1
Our scheduling heuristic can be extended to handle an arbitrary communication network.
 
2
The LDW operations load data from the memory to registers. The ADD and SSUB operations perform addition and subtraction.
 
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Metadaten
Titel
Instruction scheduling with k-successor tree for clustered VLIW processors
verfasst von
Xuemeng Zhang
Hui Wu
Jingling Xue
Publikationsdatum
01.06.2013
Verlag
Springer US
Erschienen in
Design Automation for Embedded Systems / Ausgabe 2/2013
Print ISSN: 0929-5585
Elektronische ISSN: 1572-8080
DOI
https://doi.org/10.1007/s10617-012-9103-0

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