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Erschienen in:
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2013 | OriginalPaper | Buchkapitel

1. Introduction to SRAM

verfasst von : Jawar Singh, Saraju P. Mohanty, Dhiraj K. Pradhan

Erschienen in: Robust SRAM Designs and Analysis

Verlag: Springer New York

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Abstract

The trend of Static Random Access Memory (SRAM) along with CMOS technology scaling in different processors and system-on-chip (SoC) products has fuelled the need of innovation in the area of SRAM design. SRAM bitcells are made of minimum geometry devices for high density and to keep the pace with CMOS technology scaling, as a result, they are the first to suffer from technology scaling induced side-effects. At the same time, success of next generation technology depends on the successful realization of SRAM. Therefore, different SRAM bitcell topologies and array architectures have been proposed in the recent past to meet the nano-regime challenges. Some of the major challenges in SRAM design includes poor stability, process variation tolerance, device degradation due to ageing and soft errors. In this chapter, introduction and importance of SRAM in memory hierarchy of a modern computer system and its peripheral circuitries have been presented. Different SRAM bitcell topologies and their merits and de-merits are also highlighted.

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Nächstes Kapitel Design Metrics of SRAM Bitcell
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Metadaten
Titel
Introduction to SRAM
verfasst von
Jawar Singh
Saraju P. Mohanty
Dhiraj K. Pradhan
Copyright-Jahr
2013
Verlag
Springer New York
Buch
Robust SRAM Designs and Analysis

Print ISBN: 978-1-4614-0817-8

Electronic ISBN: 978-1-4614-0818-5

Copyright-Jahr: 2013

DOI
https://doi.org/10.1007/978-1-4614-0818-5_1

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