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Erschienen in:
1998 | OriginalPaper | Buchkapitel
Introduction
verfasst von : Mukund Sivaraman, Andrzej J. Strojwas
Erschienen in: A Unified Approach for Timing Verification and Delay Fault Testing
Verlag: Springer US
Enthalten in: Professional Book Archive
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Continuing advances in design techniques and fabrication process technology are resulting in the design and manufacture of very high speed digital systems. Digital system operation at high clock speeds does not allow for much design margin, so these circuits have to be designed under very tight timing constraints. In such a scenario, it is imperative to verify the temporal behavior of such circuit designs before they are sent for fabrication. It is also equally important to test each fabricated chip to ensure that the circuit indeed performs correctly at the specified clock speed.