nach oben

Erschienen in:

2021 | OriginalPaper | Buchkapitel

1. Introduction

verfasst von : Sebastian Huhn, Rolf Drechsler

Erschienen in: Design for Testability, Debug and Reliability

Verlag: Springer International Publishing

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config

KI-gestützte Suche

Aus

Abstract

For several years, the design and fabrication of ICs no longer aim at producing devices, which fulfill one dedicated task. Instead, highly complex application scenarios are targeted, which require several heterogeneous functions to be jointly implemented on-chip at once. For this purpose, SoC designs have been successfully designed, which hold several nested modules, which inevitably lead to increasing complexity in the sense of transistor count. One important step towards this is the on-going reduction of the feature size of the used technology node, which implies that a single transistor is heavily shrunk.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

über 102.000 Bücher
über 537 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Finance + Banking
Management + Führung
Marketing + Vertrieb
Maschinenbau + Werkstoffe
Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

über 67.000 Bücher
über 390 Zeitschriften

aus folgenden Fachgebieten:

Automobil + Motoren
Bauwesen + Immobilien
Business IT + Informatik
Elektrotechnik + Elektronik
Energie + Nachhaltigkeit
Maschinenbau + Werkstoffe

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Nächstes Kapitel Integrated Circuits

[BA13]

M. Bushnell, V. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits (Springer, 2013). https://doi.org/10.1007/b117406

[Bie+99b]

A. Biere et al., Symbolic model checking without BDDs, in Proceedings of the International Conference on Tools and Algorithms for the Construction and Analysis of Systems (Springer, 1999), pp. 193–207. https://doi.org/10.1007/3540490590_14

[Bla+08]

D. Blaauw et al., Razor II: In situ error detection and correction for PVT and SER tolerance, in Proceedings of the IEEE International Conference on Solid-State Circuits (2008), pp. 400–622. https://doi.org/10.1109/ISSCC.2008.4523226

[BW89]

A.E. Barbour, A.S. Wojcik, A general constructive approach to fault-tolerant design using redundancy. IEEE Trans. Comput. 38(1), 15–29 (1989). https://doi.org/10.1109/12.8727 MathSciNetCrossRef

[Coo71]

S.A. Cook, The complexity of theorem-proving procedures, in Proceedings of the ACM International Symposium on the Theory of Computing (Shaker Heights, Ohio, USA, 1971), pp. 151–158. https://doi.org/10.1145/800157.805047

[Dre+09]

R. Drechsler et al., Test Pattern Generation Using Boolean Proof Engines (Springer, 2009). https://doi.org/10.1007/978-90-481-2360-5

[Eld59]

R.D. Eldred, Test routines based on symbolic logical statements. J. ACM 6(1), 33–37 (1959). https://doi.org/10.1145/320954.320957 MathSciNetCrossRef

[Ern+03]

D. Ernst et al., Razor: a low-power pipeline based on circuit-level timing speculation, in Proceedings of the IEEE/ACM International Symposium on Microarchitecture (2003), pp. 7–18. https://doi.org/10.1109/MICRO.2003.1253179

[EWD13]

S. Eggersglüß, R. Wille, R. Drechsler, Improved SAT-based ATPG: More constraints, better compaction, in Proceedings of the International Conference on Computer-Aided Design (2013), pp. 85–90. https://doi.org/10.1109/ICCAD.2013.6691102

[GNR64]

J.M. Galey, R.E. Norby, J.P. Roth, Techniques for the diagnosis of switching circuit failures. IEEE Trans. Commun. Electron. 83(74), 509–514 (1964) https://doi.org/10.1109/TCOME.1964.6539498 CrossRef

[HED16a]

S. Huhn, S. Eggersglüß, R. Drechsler, Leichtgewichtige Datenkompressions-Architektur für IEEE-1149.1-kompatible Testschnittstellen, in Informal Proceedings of the GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (2016)

[HED16b]

S. Huhn, S. Eggersglüß, R. Drechsler, VecTHOR: Low-cost compression architecture for IEEE-1149.1-compliant TAP controllers, in Proceedings of the IEEE European Test Symposium (2016), pp. 1–6. https://doi.org/10.1109/ETS.2016.7519303

[HED17]

S. Huhn, S. Eggersglüß, R. Drechsler, Reconfigurable TAP controllers with embedded compression for large test data volume, in Proceedings of the IEEE Defect and Fault Tolerance in VLSI and Nanotechnology Systems (2017), pp. 1–6. https://doi.org/10.1109/DFT.2017.8244462

[HED19]

S. Huhn, S. Eggersglüß, R. Drechsler, Enhanced Embedded Test Compression Technique For Processing Incompressible Test Patterns. Informal Proceedings of the GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (2019)

[HTD19a]

S. Huhn, D. Tille, R. Drechsler, A hybrid embedded multi-channel test compression architecture for low-pin count test environments in safety-critical systems, in Proceedings of the International Test Conference in Asia (2019), pp. 115–120. https://doi.org/10.1109/ITC-Asia.2019.00033

[HTD19b]

S. Huhn, D. Tille, R. Drechsler, Hybrid architecture for embedded test compression to process rejected test patterns, in Proceedings of the IEEE European Test Symposium (2019), pp. 1–2. https://doi.org/10.1109/ETS.2019.8791508

[Huh+17a]

S. Huhn et al., Enhancing robustness of sequential circuits using application-specific knowledge and formal methods, in Proceedings of the Asia and South Pacific Design Automation Conference (2017), pp. 182–187. https://doi.org/10.1109/ASPDAC.2017.7858317

[Huh+17b]

S. Huhn et al., Optimization of retargeting for IEEE 1149.1 TAP controllers with embedded compression, in Proceedings of the IEEE Design, Automation and Test in Europe (2017), pp. 578–583. https://doi.org/10.23919/DATE.2017.7927053

[Huh+18]

S. Huhn et al., A Codeword-Based Compaction Technique for On-Chip Generated Debug Data Using Two-Stage Artificial Neural Ntworks. Informal Proceedings of the GI/GMM/ITG Workshop für Testmethoden und Zuverlässigkeit von Schaltungen und Systemen (2018)

[Huh+19]

S. Huhn et al., Determing application-specific knowledge for improving robustness of sequential circuits. IEEE Trans. Very Large Scale Integr. Syst., 875–887 (2019). https://doi.org/10.1109/TVLSI.2018.2890601

[Cor11]

Intel Corporation, The Story of the Intel 4004 - Intel’s First Microprocessor, 02/22/2020 (2011). https://www.intel.de/content/www/de/de/history/museum-story-of-intel-4004.html

[Lar92]

T. Larrabee, Test pattern generation using Boolean satisfiability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(1), 4–15 (1992). https://doi.org/10.1109/43.108614 CrossRef

[Moo65]

G.E. Moore, Cramming more components onto integrated circuits. Electronics 38(8), 539–535 (1965)

[Muj19]

H. Mujtaba, AMD 2nd Gen EPYC Rome Processors Feature A Gargantuan 39.54 Billion Transistors, IO Die Pictured in Detail, 02/15/2020 (2019). https://wccftech.com/amd-2nd-gen-epyc-rome-iod-ccd-chipshots-39-billion-transistors/

[Raj+04]

J. Rajski et al., Embedded deterministic test. IEEE Trans. VLSI Syst. 23(5), 776–792 (2004). https://doi.org/10.1109/TCAD.2004.826558

[Rot66]

J.P. Roth, Diagnosis of automata failures: A calculus and a method IBM J. Res. Dev. 10(4), 278–291 (1966). https://doi.org/10.1147/rd.104.0278 MATH

[SB89]

C.E. Stroud, A.E. Barbour, Design for testability and test generation for static redundancy system level fault-tolerant circuits, in Proceedings of the International Test Conference (1989), pp. 812–818. https://doi.org/10.1109/TEST.1989.82370

Titel: Introduction
verfasst von: Sebastian Huhn
Rolf Drechsler
Verlag: Springer International Publishing
Buch: Design for Testability, Debug and Reliability
Print ISBN: 978-3-030-69208-7

Electronic ISBN: 978-3-030-69209-4

Copyright-Jahr: 2021
DOI: https://doi.org/10.1007/978-3-030-69209-4_1

Neuer Inhalt

Bildnachweise

VDI-Icon, Profil Icon, inhalt2, Springer Professional Modul/© Springer Fachmedien Wiesbaden GmbH, Nachhaltigkeitsaward Key Visual/© Cometis AG/Global ESG Monitor | Daniel Rupp | Generiert mit KI, Search Icon, Banner Hanser, Jonas Klose/© Pine Valley Capital GmbH, Carina Kießling von der Strategieberatung Roland Berger/© Monika Walther Fotografie | ATZ, Beijing Auto Show 2024: Deutsche Hersteller wollen angreifen./© EKH-Pictures / Generated with AI / Stock.adobe.com, Zeitschrift Wissensmanagement Cover, PatentFit-Logo/© Springer Fachmedien Wiesbaden GmbH, Zukunftswerkstatt Sales Excellence 2024/© AndreyPopov / Getty Images / iStock, 2023_Antrieb/© supervisuell, ATZ-Webinar: Prototypenfreie Entwicklung durch Offline- und Driver-in-the-Loop-HiL-Tests /© (c) VI-grade

Springer Professional

Abstract

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Springer Professional "Technik"

Neuer Inhalt

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.

Bitte loggen Sie sich ein, um Zugang zu Ihrer Lizenz zu erhalten.