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2019 | OriginalPaper | Buchkapitel

6. Lab-on-Chip Silicon Photonic Sensor

verfasst von : Mahmoud S. Rasras, Osama Al Mrayat

Erschienen in: The IoT Physical Layer

Verlag: Springer International Publishing

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Abstract

We propose a design of a compact photonic sensor based on two cascaded rings in a Vernier configuration integrated with a low-resolution flat-top planar echelle grating (PEG) de-multiplexer. The Vernier rings are composed of a filter and sensor rings. The sensor maps discrete changes in the index contrast, due to the presence of a target analyte, to a set of de-multiplexer channels. The channel number with highest transmittance is directly proportional to the incremental change of the effective index. Optical characteristics at different free spectral ranges (FSRs), ranging from 1 nm to 10 nm, have been studied. For example, if a filter ring FSR of 5 nm is selected, the corresponding sensor ring and de-multiplexer FSR are 4.7 and 5 nm, respectively, whereas the limit of detection (LOD) is \(620\times 10^{-6}\) RIU and \(1500\times 10^{-6}\) RIU for a ring round-trip loss of 0.1 and 0.72 dB, respectively. Meanwhile, higher sensitivity can be achieved for 1 nm FSR, where the corresponding LODs are \(160\times 10^{-6}\) RIU and \(300\times 10^{-6}\) RIU, respectively. Furthermore, by using a thermo-optic phase shift tuner, an ultra-low LOD down to \(80\times 10^{-6}\) RIU can be achieved.

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Metadaten
Titel
Lab-on-Chip Silicon Photonic Sensor
verfasst von
Mahmoud S. Rasras
Osama Al Mrayat
Copyright-Jahr
2019
DOI
https://doi.org/10.1007/978-3-319-93100-5_6

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