Languages, Design Methods, and Tools for Electronic System Design

Modern vehicles require powerful multi- and many-core hardware platforms to fulfill the demands of upcoming computationally intensive advanced driver assistance systems. Nonetheless, the resulting network-distributed electrical system architecture poses an unbearable design complexity. Furthermore, HW/SW functional security has become the number one priority in the recent years. For this reason new functional safety standards have arisen posing strict requirements on vehicular system design methodologies. Although these requirements tend to achieve full correctness of the electrical system, they also make it extremely difficult to rapidly and comprehensively close the development-evaluation-debugging cycle. Virtual prototyping is a highly promising technique to overcome these complications by providing full hardware/software visibility, controllability and adequate simulation speed at electronic system level. But the simulation of highly heterogeneous systems, such as vehicles, also requires the capability to capture and integrate interactions beyond the hardware/software domain, which limits the usage of virtual platforms. To bridge this gap, this chapter presents several methods to facilitate the integration of virtual platforms into such complex heterogeneous simulation systems via the Functional Mock-Up Interface (FMI), the de facto co-simulation standard for automotive. Since the proposed holistic simulation approach covers cross-domain interactions of the vehicular subsystems, the depth of functional safety testing, and thus overall HW/SW system robustness, can be significantly increased.

The functional mockup interface (FMI) is a tool independent standard to support model exchange and co-simulation, as intended by the automotive industry to unify the exchange of simulation models between suppliers and OEMs. The standard defines functional mockup units (FMU) as components which implement the FMI. The creation and exchange of simulation models with customers and suppliers across the automotive supply chain is highly beneficial: In order to support early phases of development (requirement formulation, creation of executable specifications, and rapid prototyping) the creation of FMUs for co-simulation is reasonable. In this paper, we propose a structured method for generation of FMUs for co-simulation which are versatile, highly transportable and fast simulating. We show how to compile FMUs based on SystemC and SystemC-AMS, representing digital as well as analog and mixed signal electric and electronic systems. This tool-independent method allows inclusion of existing simulation models with only minimal adaptations. Additionally, no modifications of the standardized libraries are necessary with the outlined approach. The resulting FMUs allow convenient exchange and fast co-simulation of automotive systems, as they may be integrated by any FMI compatible master tool. An automotive battery system use case is shown to highlight these advantages and to demonstrate the simulation performance of the resulting FMUs.

Partial Reconfiguration is one of the most attractive features of FPGAs. This feature provides new computing possibilities such as the reduction of the total area required in a FPGA, by means of functioning overlapping, or the modification of the design after its deployment, without the need of configuring completely the system and, therefore, stop its operation. However, the design of partial reconfigurable systems is still a complex task. This work focuses on facilitating the design process of dynamic partially reconfigurable systems and proposes a new development framework using high-level UML/MARTE models. Simulation and VHDL implementation code are generated from these close-to-solution-domain models, according to the specification requirements of the reconfigurable hardware captured in the specifications. To demonstrate this approach, an edge detection-based use case has been implemented with the developed framework showing an efficient outcome and achieving an accurate estimation of resources and expected performance.

A common use for Field-Programmable Gate Arrays (FPGAs) is the implementation of hardware accelerators. A way of doing so is to specify the internal logic of such accelerators by using Hardware Description Languages (HDLs). However, HDLs rely on the expertise of developers and their knowledge about hardware development with FPGAs. Regarding this, efforts have been focused on developing High-Level Synthesis (HLS) tools in an attempt to increase the overall abstraction level required for using FPGAs. However, the solutions presented by such tools are commonly considered inefficient in comparison to the ones achieved by a specialized hardware designer. An alternative solution to program FPGAs is the use of Domain-Specific Languages (DSLs), as they can provide higher abstraction levels than HDLs still allowing the developers to deal with specific issues leading to more efficient designs and not always covered by HLS tools. In this chapter we present our recent work on a DSL named LALP (Language for Aggressive Loop Pipelining), which has been designed focusing on the development of FPGA-based, aggressively pipelined, hardware accelerators. We present the recent LALP extensions and the challenges we are facing regarding to the compilation of LALP to FPGAs.

In the context of industrial size circuits, the interconnection of many blocks from many sources lead to globally asynchronous locally synchronous designs. The transmission of information between clock domains requires complex synchronizers, the correctness of which must be thoroughly verified. Current EDA tools are able to recognize predefined synchronizing modules, but fail to identify custom synchronizers. This paper presents a new model and a set of properties to automatically extract synchronizers in a flat design, and formally verify the correctness of the implemented synchronization protocol.

Virtual prototyping of integrated mixed-signal smart-sensor systems requires high-performance co-simulation of analog frontend circuitry with complex digital controller hardware and embedded real-time software. We use SystemC/TLM 2.0 in conjunction with a cycle-count accurate temporal decoupling approach (TD) to simulate digital components and firmware code execution at high speed while preserving clock-cycle accuracy and, thus, real-time behavior at time quantum boundaries. Optimal time quanta ensuring real-time capability can be calculated and set automatically during simulation if the simulation engine has access to exact timing information about upcoming inter-process communication events. These methods fail in the case of non-deterministic, asynchronous events, resulting in potentially invalid simulation results. In this paper, we propose an extension to the case of asynchronous events generated by blackbox sources from which a priori event timing information is not available, such as coupled analog simulators or hardware in the loop. Additional event processing latency or rollback effort caused by temporal decoupling is minimized by calculating optimal time quanta dynamically in a SystemC model using a linear prediction scheme. We analyze the theoretical performance of the presented predictive temporal decoupling approach (PTD) by deriving a cost model that expresses the expected simulation effort in terms of key parameters such as time quantum size and CPU time per simulation cycle. For an exemplary smart-sensor system model, we show that quasi-periodic events that trigger activities in TD processes are handled accurately after the predictor has settled.

In this chapter we propose a new power model that for the first time allows to estimate instantaneous power consumption of AMS-circuits at the system level of abstraction, by extending the state-machine based power estimation method. For this purpose, we model power consumption in power states by statistical model, and in state-transitions by a transfer function. With the help of the new model, signal-integrity issue from power distribution grid, e.g. potential disturbances due to crosstalk or ground bounce, which in the past can not be completely addressed until layout, can now be verified at the early stage of the design phase. The proposed power model is implemented as part of a simulation framework, which uses SystemC-AMS, and is applied in designing a battery management IC.