nach oben

2011 | Buch

Kapitel lesen Erstes Kapitel lesen

Three Dimensional System Integration

IC Stacking Process and Design

herausgegeben von: Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic

Verlag: Springer US

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

Einloggen, um Zugang zu erhalten

Über dieses Buch

Three-dimensional (3D) integrated circuit (IC) stacking is the next big step in electronic system integration. It enables packing more functionality, as well as integration of heterogeneous materials, devices, and signals, in the same space (volume). This results in consumer electronics (e.g., mobile, handheld devices) which can run more powerful applications, such as full-length movies and 3D games, with longer battery life. This technology is so promising that it is expected to be a mainstream technology a few years from now, less than 10-15 years from its original conception. To achieve this type of end product, changes in the entire manufacturing and design process of electronic systems are taking place. This book provides readers with an accessible tutorial on a broad range of topics essential to the non-expert in 3D System Integration. It is an invaluable resource for anybody in need of an overview of the 3D manufacturing and design chain.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction to Three-Dimensional Integration

Abstract

The semiconductor industry has been one of the main enablers for the boom of the information technology revolution that we have witnessed in the beginning of the twenty-first century. Each new generation of consumer electronics devices that hits the shelves boasts more features and functionality, better connection to other devices, lower cost, and better power efficiency per function. An excellent example of this trend is the evolution of the mobile phone since its proliferation in the end of the last century. Mobile phones started out by offering the minimal functionality of voice calling, then evolved to offering short messaging services and since then the features have kept piling up. State-of-the-art mobile phones in 2010 are in reality computing platforms offering extreme power efficiency, small form factor, and low cost for the offered functionality, which includes connectivity with virtually all known standards, high definition video decoding, social networking, office productivity suites, GPS plus any application the software community generates!

Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic

Chapter 2. TSV-Based 3D Integration

Abstract

Theoretical studies in the 1980s [1, 2] suggested that significant reductions in signal delay and power consumption could be achieved with 3D integrated circuits (3D ICs). A 3D IC is a chip that consists of multiple tiers of thinned-active 2D integrated circuits (2D ICs) that are stacked, bonded, and electrically connected with vertical vias formed through silicon or oxide layers and whose placement within the tiers is discretionary. The term “tier” is used to distinguish the transferred layers of a 3D IC from design and physical layers and is the functional section of a chip or wafer that consists of the active silicon, the interconnect, and, for a silicon-on-oxide (SOI) wafer, the buried oxide (BOX). The basic features of a 3D IC are illustrated in Fig. 2.1 in a symbolic drawing along with a cross-section of an actual 3D IC. The TSV (through silicon via) is an essential feature of the 3D IC technology and is the vertical-electrical connection formed between tiers and through silicon or oxide. A TSV is formed by aligning, defining, and etching a cavity between two tiers to expose an electrode in the lower tier; lining the sidewalls of the cavity with an insulator; and filling the cavity with metal or doped polysilicon to complete the connection. A TSV drawing and a cross-section of a TSV are shown in Fig. 2.2.

James Burns

Chapter 3. TSV Characterization and Modeling

Abstract

The through-silicon via (TSV) is composed of a conductor, also named “nail” or “plug,” crossing the Si substrate of the stacked dies [1, 2], as shown in Fig. 3.1. The conductor [common material choices include copper (Cu), tungsten (W), and polysilicon] is electrically insulated from the substrate by a dielectric layer (usually SiO₂) and interconnects the metal wires of the stacked dies.

Michele Stucchi, Guruprasad Katti, Dimitrios Velenis

Chapter 4. Homogeneous 3D Integration

Abstract

This chapter focuses on homogeneous 3D integration – that is, the vertical assembly of like materials or components – but also provides information about homogeneous 3D assemblies in combination with other 2D or 3D devices. One example of homogeneous integration is the stacking of memory layers to create a 3D memory device. In such a device, the component layers are usually made of the same material and are often virtually identical in design. This chapter uses 3D DRAM as a reference application.

Robert Patti

Chapter 5. 3D Physical Design

Abstract

The physical design process for 3D ICs is similar to that used for the traditional 2D physical design, in a sense that it transforms the circuit representation from a netlist into a geometric representation by the steps of floorplanning, placement, and routing. While the multiple-layer metals have already had 3D structure in traditional ICs for interconnects, the 3D IC technologies allow multiple layers of logical devices to be integrated in the third dimension by bonding stacks of multiple “tiers” to form 3D chips. Each tier, which is similar to a traditional 2D IC, consists of one silicon layer and several metal layers, and different tiers are connected by through-silicon vias (TS via).

Jason Cong, Guojie Luo

Chapter 6. Co-optimization of Power, Thermal, and Signal Interconnect for 3D ICs

Abstract

Historically, advances in the field of packaging and system integration have not progressed at the same rate as ICs. In fact, today’s silicon ancillary technologies have truly become a limiter to the performance gains possible from advances in semiconductor manufacturing, especially due to cooling, power delivery, and signaling [1, 2]. Today, it is widely accepted that three-dimensional (3D) system integration is a key enabling technology and has recently gained significant momentum in the semiconductor industry. Three-dimensional integration may be used either to partition a single chip into multiple strata to reduce on-chip global interconnect lengths [3] and/or used to stack chips that are homogeneous or heterogeneous. AQ: Please check if the inserted citation of Fig. 6.1 is appropriate.

Young-Joon Lee, Michael Healy, Sung Kyu Lim

Chapter 7. PathFinding and TechTuning

Abstract

This chapter discusses various implications of the 3D integration technology on the design methodologies, flows, and associated tools. The experiences from the advanced 2D technologies are extrapolated and combined with the incremental challenges posed by the 3D technologies, and the requirements for design ecosystem for 3D technologies are precipitated. The chapter is organized in five sections. In the first section, we define the overall requirements for the 3D design ecosystem, and we identify the need for two incremental design methodologies, in addition to the traditional design authoring flow. The second section describes one of the incremental design methodologies – named PathFinding, and the third section discusses the other methodology – named TechTuning. In section four we present practical application of the proposed design methodology and associated tool chain. Section 5 gives a brief summary and few concluding remarks.

Dragomir Milojevic, Ravi Varadarajan, Dirk Seynhaeve, Pol Marchal

Chapter 8. 3D Stacking of DRAM on Logic

Abstract

An ever-increasing number of transistors are being placed onto silicon dies in both small and large computing systems. The shrinking of the transistors on these chips has allowed an increasingly large amount of computing power to be brought to smaller and smaller devices. There have been many advances in computing architectures that have allowed this pace to continue. Examples can be seen through the development of combining numerous application processors into MPSoCs (multiprocessor systems on a chip) as well as techniques like hardware multithreading. Through the increase in both complexity of chip designs and the number of those chips occupying a single die, our computers now require greater bandwidth to an ever increasing amount of system DRAM memory. By optimizing these systems with TSVs, one can alleviate this memory bottleneck while simultaneously reducing the overall energy consumption of the complete computing platform.

Trevor Carlson, Marco Facchini

Chapter 9. Microprocessor Design Using 3D Integration Technology

Abstract

Previous chapters have described various aspects of 3D integration technology, including the fundamentals of process technology and EDA design flows for 3D IC design. In this chapter, we discuss how to leverage the emerging 3D integration technology for future microprocessor design.

Yuan Xie

Chapter 10. 3D Through-Silicon Via Technology Markets and Applications

Abstract

The drivers for through-silicon via (TSV) adoption can be divided into two major application areas. The first is products driven by form factor requirements. In some cases, this is also coupled with performance advantages. The second is high-performance computing, where the adoption of 3D TSV technology promises higher clock rates, lower power dissipation, and higher integration density. The technology will be adopted in many high-performance computing applications because it solves issues related to electrical performance, memory latency, power, and noise on and off the chip. For some applications, a high-bandwidth memory interface to the logic has been the main driver for the development of the technology [1].

E. Jan Vardaman

Backmatter

Titel: Three Dimensional System Integration
herausgegeben von: Antonis Papanikolaou
Dimitrios Soudris
Riko Radojcic
Verlag: Springer US
Electronic ISBN: 978-1-4419-0962-6
Print ISBN: 978-1-4419-0961-9
DOI: https://doi.org/10.1007/978-1-4419-0962-6