Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
ATZ-Fachkongress

Chassis.tech plus 2024


4 Kongresse in einer Veranstaltung

Treffen Sie in München die Fachleute von Chassis, Lenkung, Bremsen sowie Reifen/Räder.
Erweiterte Suche
Anmelden
nach oben

2016 | Buch

Introduction Kapitel lesen Erstes Kapitel lesen

Memory Controllers for Mixed-Time-Criticality Systems

Architectures, Methodologies and Trade-offs

verfasst von: Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens

Verlag: Springer International Publishing

Buchreihe : Embedded Systems

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik"

Einloggen, um Zugang zu erhalten
insite
SUCHEN

Über dieses Buch

This book discusses the design and performance analysis of SDRAM controllers that cater to both real-time and best-effort applications, i.e. mixed-time-criticality memory controllers. The authors describe the state of the art, and then focus on an architecture template for reconfigurable memory controllers that addresses effectively the quickly evolving set of SDRAM standards, in terms of worst-case timing and power analysis, as well as implementation. A prototype implementation of the controller in SystemC and synthesizable VHDL for an FPGA development board are used as a proof of concept of the architecture template.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction
Abstract
In this chapter, we first look at the developments and trends that led to the current way of working with SDRAM in Sects. 1.1–1.4. We then identify the requirements on a modern SDRAM controller in Sect. 1.5, and capture them in the problem statement in Sect. 1.6. Here, we also briefly discuss how the contributions of this book address the raised issues. Finally, we link the contributions to the remaining chapters in Sect. 1.7.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 2. Reconfigurable Real-Time Memory Controller Architecture
Abstract
Background information on SDRAM technology is provided in Sect. 2.1. The properties of pattern-based memory controllers are introduced in Sect. 2.2. The story continues with a detailed description of our novel reconfigurable memory controller architecture in Sect. 2.3. In Sect. 2.4, we derive a worst-case performance model for this memory controller architecture, based on a Latency-rate server abstraction. We then continue with a discussion on the implementation of a hardware instance on FPGA in Sect. 2.5, followed by a cost evaluation in Sect. 2.6.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 3. Memory Patterns
Abstract
This chapter provides a memory controller template that is not bound to a specific memory device or SDRAM type. For this purpose, we introduce a memory pattern generation algorithm that is easily transferable across SDRAM types (DDR2/3/4 and LPDDR1/2/3). Section 3.1 describes the abstraction step that allows us to do this. Section 3.2 applies this abstraction in the form of a parameterized pattern-generation heuristic, which is later refined to improve its effectiveness for DDR4 memories. A predictable pattern set can be converted into a composable pattern set to create a composable memory resource, as we show in Sect. 3.3. At the end of this chapter, in Sect. 3.4, we first introduce the set of memory devices that are used to evaluate the effectiveness of the pattern-generation heuristics. Finally, we use the FPGA instance of our memory controller to demonstrate how using composable patterns isolates the timing behavior of two co-running applications.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 4. Cycle-Accurate SDRAM Power Modeling
Abstract
SDRAM memories contribute significantly to the overall system power and energy consumption of a system and require effective power management for their energy efficient use. The key prerequisite to their efficient power/energy management is to use accurate SDRAM power and energy consumption estimates. This chapter addresses this issue by proposing a high-level cycle-accurate SDRAM power model called DRAMPower, which employs JEDEC-specified current measures and performs high-precision modeling of SDRAM operations to obtain accurate power and energy estimates. We compare and contrast the state of the art in high-level SDRAM power models against ours, and show how we improve the precision of the modeling of the different SDRAM operations, state transitions and power-saving modes.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 5. Power/Performance Trade-Offs
Abstract
A range of possible memory patterns can be generated within the design space provided by the BI and BC parameters that were discussed in Chap. 3. Here, we evaluate the effect of BI and BC on bandwidth, energy, and power. This chapter first describes how these metrics are calculated in Sect. 5.1. Section 5.2 applies these calculations to twelve memories from six SDRAM generations. The observed trends and trade-offs between 16 different pattern configurations and memory modules, both within and across generations, are discussed here as well. Section 5.3 looks at the influence of (BI, BC) on the worst-case response time of an atom. Finally, in Sect. 5.4, we apply the worst-case bandwidth analysis to the Raptor instance of the memory controller, and we experimentally show that its behavior accurately matches the worst-case model.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 6. Conservative Open-Page Policy
Abstract
This chapter introduces a version of an open-page policy that does not compromise on worst-case guarantees, and can hence be freely used by controllers that care about both worst-case and average-case performance. Section 6.1 explains the intuition behind it, and introduces terminology. Section 6.2 discusses the impact of the policy on the previously introduced controller architecture. The implementation of the policy is refined in Sect. 6.3, such that the average-case performance gains are improved. Section 6.4 evaluates the effectiveness of the policy through experiments with the SystemC instance of the memory controller, followed by conclusions in Sect. 6.5.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 7. Reconfiguration
Abstract
Systems generally operate in dynamic environments where the mix of active applications or use-case is not constant during the execution. This chapter shows how the configuration of our memory controller is adaptable to these changes, starting with an overview of the reconfiguration options offered by our architecture in Sect. 7.1. Section 7.2 describes how predictable and composable performance guarantees are defined for clients that remain active during reconfiguration, and Sect. 7.3 discusses the implication this has on the reconfiguration options we can safely use for these clients. Reconfiguring an arbiter while retaining predictable performance guarantees is not trivial: Sect. 7.4 shows how to construct and use a TDM arbiter that has this property. Section 7.5 evaluates the contributions in this chapter through experiments with our SystemC model and the VHDL instance of our controller.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 8. Related Work
Abstract
This chapter describes related work, and is split into three main sections. The first one, Sect. 8.1, discusses various approaches toward the construction and analysis of SDRAM controllers. Section 8.2 considers performance-overviews for SDRAM memories, while Sect. 8.3 discusses other approaches towards run-time reconfiguration of (shared) resources under real-time constraints.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Chapter 9. Conclusions and Future Work
Abstract
In this chapter, we look back at what we have done in this book. Section 9.1 briefly discussed the motivation behind the work, and lists the main contributions from Chaps. 2–7. Additionally, we provide a slightly broader perspective on the presented content and its relation to the research field in which we operate. This leads to suggestions for future research directions in Sect. 9.2.
Sven Goossens, Karthik Chandrasekar, Benny Akesson, Kees Goossens
Backmatter
Metadaten
Titel
Memory Controllers for Mixed-Time-Criticality Systems
verfasst von
Sven Goossens
Karthik Chandrasekar
Benny Akesson
Kees Goossens
Copyright-Jahr
2016
Electronic ISBN
978-3-319-32094-6
Print ISBN
978-3-319-32093-9
DOI
https://doi.org/10.1007/978-3-319-32094-6

Neuer Inhalt

    Bildnachweise