Quality-Driven SystemC Design

verfasst von: Daniel Große, Rolf Drechsler

Verlag: Springer Netherlands

Enthalten in: Springer Professional "Wirtschaft+Technik" , Springer Professional "Technik" , Springer Professional "Wirtschaft"

Einloggen, um Zugang zu erhalten

Über dieses Buch

A quality-driven design and verification flow for digital systems is developed and presented in Quality-Driven SystemC Design. Two major enhancements characterize the new flow: First, dedicated verification techniques are integrated which target the different levels of abstraction. Second, each verification technique is complemented by an approach to measure the achieved verification quality. The new flow distinguishes three levels of abstraction (namely system level, top level and block level) and can be incorporated in existing approaches. After reviewing the preliminary concepts, in the following chapters the three levels for modeling and verification are considered in detail. At each level the verification quality is measured. In summary, following the new design and verification flow a high overall quality results.

Inhaltsverzeichnis

Frontmatter

Chapter 1. Introduction

Abstract

Over the last decades electronic systems have become more and more AQ1 important. Nowadays, they play a major role for example in communication, consumer electronic and safety–critical applications. From the design perspective this leads to very diverse requirements. For instance, a design aspect is high computing power as in case of personal computers. For mobile devices like modern cell phones or PDAs rich functionality is the central aspect. In contrast, for safety–critical systems as for example found in automobiles, airplanes or medical devices the design correctness is most important.

Overall the growth of electronic systems is due to the continued advance in the fabrication technology of integrated circuits. As predicted by Gordon Moore in 1965 the number of transistors per chip doubles every 18 months. This exponential growth leads to huge problem instances that have to be handled during the design of a system. For example, Intel has been able to build a processor consisting of 2 billion transistors: Tukwila is scheduled for production in the first quarter of 2010 [Int09].

Daniel Große, Rolf Drechsler

Chapter 2. Preliminaries

Abstract

In this chapter the basic notations and definitions are given to make this book self-contained. In the first part Boolean reasoning including state-of the-art proof techniques are reviewed. Then, circuits and their respective representation are introduced. Thereafter, the two typical scenarios of formal verification are described, i.e. equivalence checking and (bounded) model checking. Finally, the basics and concept of the system description language SystemC are given.

The presentation is always given in a compact way, but references for further reading are provided.

Daniel Große, Rolf Drechsler

Chapter 3. System-Level Verification

Abstract

The parts of the proposed design and verification flow covered in this chapter are shown in Figure 3.1. As already mentioned, for modeling a system in this book the system description language SystemC is used. Thus, from the textual specification the initial system-level model is directly described in SystemC. Following the design methodology of SystemC the system-level model is very abstract and can be simulated at this high level of abstraction already by compiling the model into the executable specification. This allows for efficient design space exploration. After analyzing the results of a certain design direction the designer can go back and revise design decisions (for simplicity this loop is not shown in the figure). Since not all details have been modeled already, this can be accomplished with moderate costs. Also part of the design space exploration phase is to check hardware/software trade-offs. Hence, hardware/software partitioning is performed to meet the requirements of the specification. During the development of the system-level model verification is started.

Daniel Große, Rolf Drechsler

Chapter 4. Block-Level Verification

Abstract

In this chapter techniques for verification at the block level are presented. Figure 4.1 shows the respective parts of the proposed design and verification flow that are described in this chapter. The motivation for considering components of the system at the block level before addressing the top level in more detail is as follows. Based on the SystemC design methodology the system is stepwise refined and finally consists of hierarchical modules (with the respective functionality) and interfaces for communication. At this point all parts of the system are synthesizable. But from the verification perspective along the refinement process until reaching the synthesizable descriptions only simulation based techniques have been used to check that the specification is met. Even with the strong constraint-based simulation methods and the complementing testbench quality check as presented in Chapter 3 typically not all design errors can be found. Thus, in the following formal methods are applied to the blocks of the design. Thereby, their functional correctness can be guaranteed.

The middle of Figure 4.1 shows the proposed verification techniques as well as the corresponding quality check for the block level. First, in this chapter a property checking approach for SystemC is presented. The approach uses the front-end of [FGC⁺04], which is part of the SystemC design environment SyCE¹ [DFGG05], to generate a Finite State Machine (FSM) representation from a SystemC description.

Daniel Große, Rolf Drechsler

Chapter 5. Top-Level Verification

Abstract

After complete formal verification at the block level – based on the techniques presented in the previous chapter – this chapter addresses the verification at the top level. The top-level verification task is required since large systems cannot be handled completely by formal methods due to complexity reasons. Thus, as introduced by the proposed design and verification flow, block-level verification is carried out first and then top-level verification starts on top of the high quality result, i.e. 100% correct proven blocks. Hence, the techniques that are presented in the following focus on the verification of the communication between the proven blocks.

The parts of the proposed design and verification flow that are covered here are depicted in Figure 5.1. In black the top-level parts are shown whereas in light gray the dependencies to the system level and the block level are illustrated, respectively. The dependencies are explained below when the respective top-level task is described.

Daniel Große, Rolf Drechsler

Chapter 6. Summary and Conclusions

Abstract

Today, the design and verification of electronic systems is a very challenging task. To cope with the steadily increasing complexity and the pressure of time to-market the design entry has been lifted to high-level descriptions, i.e. the level of abstraction for designing systems has been raised. In this book a prominent design flow based on the system description language SystemC was considered. However, while the single-language concept of the SystemC design flow allows a continuous modeling from system level down to synthesizable descriptions, only low verification quality is achieved. There are two main reasons: First, the existing verification techniques are decoupled and are often based on simple simulation techniques. Second, the resulting verification quality in terms of the covered functionality is not ensured automatically along the refinement process. Therefore, a quality-driven design and verification flow was developed in this book. The “traditional” SystemC design flow is enhanced by 1. Dedicated verification techniques which target each level of abstraction and employ formal methods where possible and 2. Complementing each verification task by measuring the resulting quality.

In the new flow three levels of abstraction for modeling of digital systems are distinguished: The system-level model that is refined to the synthesizable top level model which again consists of several block-level models.

Daniel Große, Rolf Drechsler

Backmatter

Titel: Quality-Driven SystemC Design
verfasst von: Daniel Große
Rolf Drechsler
Verlag: Springer Netherlands
Electronic ISBN: 978-90-481-3631-5
Print ISBN: 978-90-481-3630-8
DOI: https://doi.org/10.1007/978-90-481-3631-5