Skip to main content
Erschienen in: Real-Time Systems 2/2014

01.03.2014

Static analysis of multi-core TDMA resource arbitration delays

verfasst von: Timon Kelter, Heiko Falk, Peter Marwedel, Sudipta Chattopadhyay, Abhik Roychoudhury

Erschienen in: Real-Time Systems | Ausgabe 2/2014

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

In the development of hard real-time systems, knowledge of the Worst-Case Execution Time (WCET) is needed to guarantee the safety of a system. For single-core systems, static analyses have been developed which are able to derive guaranteed bounds on a program’s WCET. Unfortunately, these analyses cannot directly be applied to multi-core scenarios, where the different cores may interfere with each other during the access to shared resources like for example shared buses or memories. For the arbitration of such resources, TDMA arbitration has been shown to exhibit favorable timing predictability properties. In this article, we review and extend a methodology for analyzing access delays for TDMA-arbitrated resources. Formal proofs of the correctness of these methods are given and a thorough experimental evaluation is carried out, where the presented techniques are compared to preexisting ones on an extensive set of real-world benchmarks for different classes of analyzed systems.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Anhänge
Nur mit Berechtigung zugänglich
Fußnoten
1
Best-Case Execution Time.
 
2
In case of out-of-order pipelines, the analysis which we will present in the following would need to consider all orders in which the instructions of basic blocks can possibly be executed in separation and merge this information afterwards to get a valid overapproximation.
 
3
Using the arithmetic mean would be infeasible since we are working with relative values here (Fleming and Wallace 1986).
 
Literatur
Zurück zum Zitat Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Addison-Wesley, Reading Aho AV, Lam MS, Sethi R, Ullman JD (2006) Compilers: principles, techniques, and tools, 2nd edn. Addison-Wesley, Reading
Zurück zum Zitat Andrei A, Eles P, Peng Z, Rosen J (2008) Predictable implementation of real-time applications on multiprocessor systems-on-chip. In: Proceedings of the 21st international conference on VLSI design, VLSID ’08. IEEE Computer Society, Washington, pp 103–110 Andrei A, Eles P, Peng Z, Rosen J (2008) Predictable implementation of real-time applications on multiprocessor systems-on-chip. In: Proceedings of the 21st international conference on VLSI design, VLSID ’08. IEEE Computer Society, Washington, pp 103–110
Zurück zum Zitat Chattopadhyay S, Roychoudhury A, Mitra T (2010) Modeling shared cache and bus in multi-cores for timing analysis. In: Proceedings of the 13th international workshop on software & compilers for embedded systems, SCOPES ’10. ACM, New York, pp 6:1–6:10 Chattopadhyay S, Roychoudhury A, Mitra T (2010) Modeling shared cache and bus in multi-cores for timing analysis. In: Proceedings of the 13th international workshop on software & compilers for embedded systems, SCOPES ’10. ACM, New York, pp 6:1–6:10
Zurück zum Zitat Cousot P, Cousot R (1979) Systematic design of program analysis frameworks. In: Proceedings of the 6th ACM SIGPLAN-SIGACT symposium on principles of programming languages (POPL), San Antonio, Texas. ACM, New York, pp 269–282 Cousot P, Cousot R (1979) Systematic design of program analysis frameworks. In: Proceedings of the 6th ACM SIGPLAN-SIGACT symposium on principles of programming languages (POPL), San Antonio, Texas. ACM, New York, pp 269–282
Zurück zum Zitat Fleming P, Wallace J (1986) How not to lie with statistics: the correct way to summarize benchmark results. Commun ACM 29:218–221 CrossRef Fleming P, Wallace J (1986) How not to lie with statistics: the correct way to summarize benchmark results. Commun ACM 29:218–221 CrossRef
Zurück zum Zitat Goossens K, Hansson A (2010) The aethereal network on chip after ten years: goals, evolution, lessons, and future. In: Proceedings of the 2010 design automation conference, Anaheim, California, USA. ACM, New York, pp 306–311 Goossens K, Hansson A (2010) The aethereal network on chip after ten years: goals, evolution, lessons, and future. In: Proceedings of the 2010 design automation conference, Anaheim, California, USA. ACM, New York, pp 306–311
Zurück zum Zitat Gustavsson A, Ermedahl A, Lisper B, Pettersson P (2010) Towards WCET analysis of multicore architectures using UPPAAL. In: 10th International workshop on worst-case execution time analysis, WCET ’10. Schloss Dagstuhl—Leibniz-Zentrum für Informatik, Dagstuhl, pp 101–112 Gustavsson A, Ermedahl A, Lisper B, Pettersson P (2010) Towards WCET analysis of multicore architectures using UPPAAL. In: 10th International workshop on worst-case execution time analysis, WCET ’10. Schloss Dagstuhl—Leibniz-Zentrum für Informatik, Dagstuhl, pp 101–112
Zurück zum Zitat Hardy D, Puaut I (2008) WCET analysis of multi-level non-inclusive set-associative instruction caches. In: Proceedings of the 2008 real-time systems symposium. IEEE Computer Society, Washington, pp 456–466 CrossRef Hardy D, Puaut I (2008) WCET analysis of multi-level non-inclusive set-associative instruction caches. In: Proceedings of the 2008 real-time systems symposium. IEEE Computer Society, Washington, pp 456–466 CrossRef
Zurück zum Zitat Hardy D, Piquet T, Puaut I (2009) Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In: Proceedings of the 2009 30th IEEE real-time systems symposium, RTSS ’09. IEEE Computer Society, Washington, pp 68–77 Hardy D, Piquet T, Puaut I (2009) Using bypass to tighten WCET estimates for multi-core processors with shared instruction caches. In: Proceedings of the 2009 30th IEEE real-time systems symposium, RTSS ’09. IEEE Computer Society, Washington, pp 68–77
Zurück zum Zitat Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2011) Bus-aware multicore WCET analysis through TDMA offset bounds. In: Proceedings of the 23rd euromicro conference on real-time systems (ECRTS), Porto/Portugal, pp 3–12 Kelter T, Falk H, Marwedel P, Chattopadhyay S, Roychoudhury A (2011) Bus-aware multicore WCET analysis through TDMA offset bounds. In: Proceedings of the 23rd euromicro conference on real-time systems (ECRTS), Porto/Portugal, pp 3–12
Zurück zum Zitat Lundqvist T, Stenström P (1999) Timing anomalies in dynamically scheduled microprocessors. In: Proceedings of the 20th IEEE real-time systems symposium, RTSS ’99. IEEE Computer Society, Washington Lundqvist T, Stenström P (1999) Timing anomalies in dynamically scheduled microprocessors. In: Proceedings of the 20th IEEE real-time systems symposium, RTSS ’99. IEEE Computer Society, Washington
Zurück zum Zitat Lv M, Guan N, Yi W, Yu G (2010) Combining abstract interpretation with model checking for timing analysis of multicore software. In: 31st IEEE real-time systems symposium (RTSS) Lv M, Guan N, Yi W, Yu G (2010) Combining abstract interpretation with model checking for timing analysis of multicore software. In: 31st IEEE real-time systems symposium (RTSS)
Zurück zum Zitat Mische J, Guliashvili I, Uhrig S, Ungerer T (2010) How to enhance a superscalar processor to provide hard real-time capable in-order SMT. In: Proceedings of the 23rd international conference on architecture of computing systems (ARCS), Hannover/Germany, pp 2–14. doi:10.1007/987-3-642-11950-7_2 Mische J, Guliashvili I, Uhrig S, Ungerer T (2010) How to enhance a superscalar processor to provide hard real-time capable in-order SMT. In: Proceedings of the 23rd international conference on architecture of computing systems (ARCS), Hannover/Germany, pp 2–14. doi:10.​1007/​987-3-642-11950-7_​2
Zurück zum Zitat Muchnick SS (1997) Advanced compiler design and implementation. Morgan Kaufmann, San Mateo Muchnick SS (1997) Advanced compiler design and implementation. Morgan Kaufmann, San Mateo
Zurück zum Zitat Nemer F, Cassé H, Sainrat P, Bahsoun JP, Michiel MD (2006) PapaBench: a free real-time benchmark. In: Mueller F (ed) 6th intl workshop on worst-case execution time (WCET) analysis, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI). Schloss Dagstuhl, Dagstuhl Nemer F, Cassé H, Sainrat P, Bahsoun JP, Michiel MD (2006) PapaBench: a free real-time benchmark. In: Mueller F (ed) 6th intl workshop on worst-case execution time (WCET) analysis, Internationales Begegnungs- und Forschungszentrum für Informatik (IBFI). Schloss Dagstuhl, Dagstuhl
Zurück zum Zitat Paolieri M, Quiñones E, Cazorla FJ, Bernat G, Valero M (2009) Hardware support for WCET analysis of hard real-time multicore systems. In: Proceedings of the 36th annual international symposium on computer architecture, ISCA ’09. ACM, New York, pp 57–68 CrossRef Paolieri M, Quiñones E, Cazorla FJ, Bernat G, Valero M (2009) Hardware support for WCET analysis of hard real-time multicore systems. In: Proceedings of the 36th annual international symposium on computer architecture, ISCA ’09. ACM, New York, pp 57–68 CrossRef
Zurück zum Zitat Paukovits C, Kopetz H (2008) Concepts of switching in the time-triggered network-on-chip. In: Proceedings of the 14th IEEE international conference on embedded and real-time computing systems and applications, pp 120–129 Paukovits C, Kopetz H (2008) Concepts of switching in the time-triggered network-on-chip. In: Proceedings of the 14th IEEE international conference on embedded and real-time computing systems and applications, pp 120–129
Zurück zum Zitat Pellizzoni R, Schranzhofer A, Chen JJ, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: Proceedings of the conference on design, automation and test in Europe, DATE ’10, pp 741–746 Pellizzoni R, Schranzhofer A, Chen JJ, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: Proceedings of the conference on design, automation and test in Europe, DATE ’10, pp 741–746
Zurück zum Zitat Pitter C, Schoeberl M (2010) A real-time Java chip-multiprocessor. ACM Trans Embed Comput Syst 10:9 CrossRef Pitter C, Schoeberl M (2010) A real-time Java chip-multiprocessor. ACM Trans Embed Comput Syst 10:9 CrossRef
Zurück zum Zitat Reineke J, Sen R (2009) Sound and efficient WCET analysis in the presence of timing anomalies. In: Holsti N (ed) 9th intl workshop on worst-case execution time (WCET) analysis. Schloss Dagstuhl—Leibniz-Zentrum für Informatik, Dagstuhl Reineke J, Sen R (2009) Sound and efficient WCET analysis in the presence of timing anomalies. In: Holsti N (ed) 9th intl workshop on worst-case execution time (WCET) analysis. Schloss Dagstuhl—Leibniz-Zentrum für Informatik, Dagstuhl
Zurück zum Zitat Reineke J, Wachter B, Thesing S, Wilhelm R, Polian I, Eisinger J, Becker B (2006) A definition and classification of timing anomalies. In: Proceedings of 6th international workshop on worst-case execution time (WCET) analysis Reineke J, Wachter B, Thesing S, Wilhelm R, Polian I, Eisinger J, Becker B (2006) A definition and classification of timing anomalies. In: Proceedings of 6th international workshop on worst-case execution time (WCET) analysis
Zurück zum Zitat Suhendra V, Mitra T (2008) Exploring locking & partitioning for predictable shared caches on multi-cores. In: Proceedings of the 45th annual design automation conference, DAC ’08. ACM, New York, pp 300–303 CrossRef Suhendra V, Mitra T (2008) Exploring locking & partitioning for predictable shared caches on multi-cores. In: Proceedings of the 45th annual design automation conference, DAC ’08. ACM, New York, pp 300–303 CrossRef
Zurück zum Zitat Wilhelm R, Engblom J, Ermedahl A, Holsti N, Thesing S, Whalley D, Bernat G, Ferdinand C, Heckmann R, Mitra T, Mueller F, Puaut I, Puschner P, Staschulat J, Stenström P (2008) The worst-case execution-time problem—overview of methods and survey of tools. ACM Trans Embed Comput Syst 7:36:1–36:53 CrossRef Wilhelm R, Engblom J, Ermedahl A, Holsti N, Thesing S, Whalley D, Bernat G, Ferdinand C, Heckmann R, Mitra T, Mueller F, Puaut I, Puschner P, Staschulat J, Stenström P (2008) The worst-case execution-time problem—overview of methods and survey of tools. ACM Trans Embed Comput Syst 7:36:1–36:53 CrossRef
Zurück zum Zitat Wilhelm R, Grund D, Reineke J, Schlickling M, Pister M, Ferdinand C (2009) Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(7):966–978 CrossRef Wilhelm R, Grund D, Reineke J, Schlickling M, Pister M, Ferdinand C (2009) Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Trans Comput-Aided Des Integr Circuits Syst 28(7):966–978 CrossRef
Zurück zum Zitat Zhang W, Yan J (2009) Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches. IEEE Computer Society Press, Los Alamitos, pp 455–463 Zhang W, Yan J (2009) Accurately estimating worst-case execution time for multi-core processors with shared direct-mapped instruction caches. IEEE Computer Society Press, Los Alamitos, pp 455–463
Metadaten
Titel
Static analysis of multi-core TDMA resource arbitration delays
verfasst von
Timon Kelter
Heiko Falk
Peter Marwedel
Sudipta Chattopadhyay
Abhik Roychoudhury
Publikationsdatum
01.03.2014
Verlag
Springer US
Erschienen in
Real-Time Systems / Ausgabe 2/2014
Print ISSN: 0922-6443
Elektronische ISSN: 1573-1383
DOI
https://doi.org/10.1007/s11241-013-9189-x

Premium Partner