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International Journal of Parallel Programming

Erschienen in:

27.09.2016

Energy-Aware Modeling of Scaled Heterogeneous Systems

verfasst von: Ami Marowka

Erschienen in: International Journal of Parallel Programming | Ausgabe 5/2017

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Abstract

Many-core processors are accelerating the performance of contemporary high-performance systems. Managing power consumption within these systems demands low-power architectures to increase power savings. One of the promising solutions offered today by microprocessor architects is asymmetric microprocessors that integrate different core architectures on a single die. This paper presents analytical models based on scaled power metrics to analyze the impact of various architectural design choices on scaled performance and power savings. The power consumption implications of different processing schemes and various chip configurations were also analyzed. Analysis shows that by choosing the optimal chip configuration, energy efficiency and energy savings can be increased considerably.

Vorheriger Artikel Guest Editorial for Hybrid Parallelism in New HPC Systems

Nächster Artikel GHOST: Building Blocks for High Performance Sparse Linear Algebra on Heterogeneous Systems

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Titel: Energy-Aware Modeling of Scaled Heterogeneous Systems
verfasst von: Ami Marowka
Publikationsdatum: 27.09.2016
Verlag: Springer US
Erschienen in: International Journal of Parallel Programming / Ausgabe 5/2017
Print ISSN: 0885-7458
Elektronische ISSN: 1573-7640
DOI: https://doi.org/10.1007/s10766-016-0453-2

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