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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 2-3/2009

01.06.2009

Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion

verfasst von: Mihir R. Choudhury, Quming Zhou, Kartik Mohanram

Erschienen in: Journal of Electronic Testing | Ausgabe 2-3/2009

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Abstract

This paper describes a tunable transient filter (TTF) design for soft error rate reduction in combinational logic circuits. TTFs can be inserted into combinational circuits to suppress propagated single-event transients (SETs) before they can be captured in latches or flip-flops. TTFs are tuned by adjusting the maximum width of the propagated SET that can be suppressed. A TTF requires 6–14 transistors, making it an attractive cost-effective option to reduce the soft error rate in combinational circuits. A global optimization approach based on geometric programming that integrates TTF insertion with dual-V DD and gate sizing is described. Simulation results for the 65 nm process technology indicate that a 17–48× reduction in the soft error rate can be achieved with this approach.
Vorheriger Artikel A New Algorithm for the Selection of Control Cells in Boundary-Scan Interconnect Test

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Metadaten
Titel
Soft Error Rate Reduction Using Circuit Optimization and Transient Filter Insertion
verfasst von
Mihir R. Choudhury
Quming Zhou
Kartik Mohanram
Publikationsdatum
01.06.2009
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 2-3/2009
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-009-5103-9

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