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Journal of Electronic Testing
Erschienen in: Journal of Electronic Testing 5/2010

01.10.2010

Efficient Concurrent Self-Test with Partially Specified Patterns

verfasst von: Michael A. Kochte, Christian G. Zoellin, Hans-Joachim Wunderlich

Erschienen in: Journal of Electronic Testing | Ausgabe 5/2010

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Abstract

Structural on-line self-test may be performed to detect permanent faults and avoid their accumulation in the system. This paper improves existing techniques for concurrent BIST that are based on a deterministic test set. Here, the test patterns are specially generated with a small number of specified bits. This results in very low test length and fault detection latency, which allows to frequently test critical faults. As a consequence, the likelihood of fault accumulation is reduced. Experiments with benchmark circuits show that the hardware overhead is significantly lower than the overhead of the state of the art. Moreover, a case-study on a super-scalar RISC processor demonstrates the feasibility of the method.
Vorheriger Artikel Design of Memories with Concurrent Error Detection and Correction by Nonlinear SEC-DED Codes

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Metadaten
Titel
Efficient Concurrent Self-Test with Partially Specified Patterns
verfasst von
Michael A. Kochte
Christian G. Zoellin
Hans-Joachim Wunderlich
Publikationsdatum
01.10.2010
Verlag
Springer US
Erschienen in
Journal of Electronic Testing / Ausgabe 5/2010
Print ISSN: 0923-8174
Elektronische ISSN: 1573-0727
DOI
https://doi.org/10.1007/s10836-010-5167-6

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