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2017 | OriginalPaper | Buchkapitel

LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits

verfasst von : Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma

Erschienen in: VLSI Design and Test

Verlag: Springer Singapore

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Abstract

Reliability and variability issues are the biggest design challenges facing nanoscale high-speed applications. Negative bias temperature instability (NBTI) is the major reliability issues with the scaled devices. Effect of NBTI increases with the time and it increases the threshold voltage of PMOS. This paper presents an NBTI degradation sensor which monitors the change in standby leakage current (\(I_{ddq}\)) of the test circuit under the stress conditions. The performance of proposed sensor is linear and highly sensitive. Due to high sensitivity, the proposed sensor is best suited for compensation of temporal degradation during measurement. The sensitivity of the proposed sensor further increase at elevated temperature (125 \(^{\circ }\)C) compares to room temperature (27 \(^{\circ }\)C). The proposed sensor has the improvement in sensitivity of 20.12% and 74.82% as compared to CM based sensor at room temperature and elevated temperature respectively. The transimpedance of the proposed sensor is linear and the linearity is unaffected by the voltage and temperature variations. The proposed sensor is 25% smaller and has faster response compared to CM based sensor. The proposed sensor is also unaffected by the supply voltage variations.

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Literatur
1.
Zurück zum Zitat Borkar, S., et al.: Microarchitecture and design challenges for gigascale integration. MICRO 37, 3 (2004) Borkar, S., et al.: Microarchitecture and design challenges for gigascale integration. MICRO 37, 3 (2004)
2.
Zurück zum Zitat Cho, M., Lee, J.D., Aoulaiche, M., Kaczer, B., Roussel, P., Kauerauf, T., Degraeve, R., Franco, J., Ragnarsson, L.Å., Groeseneken, G.: Insight into N/PBTI mechanisms in sub-1-nm-EOT devices. IEEE Trans. Electron Devices 59(8), 2042–2048 (2012)CrossRef Cho, M., Lee, J.D., Aoulaiche, M., Kaczer, B., Roussel, P., Kauerauf, T., Degraeve, R., Franco, J., Ragnarsson, L.Å., Groeseneken, G.: Insight into N/PBTI mechanisms in sub-1-nm-EOT devices. IEEE Trans. Electron Devices 59(8), 2042–2048 (2012)CrossRef
3.
Zurück zum Zitat Panagopoulos, G.D., Roy, K.: A three-dimensional physical model for \(V_{th}\) variations considering the combined effect of NBTI and RDF. IEEE Trans. Electron Devices 58(8), 2337–2346 (2011)CrossRef Panagopoulos, G.D., Roy, K.: A three-dimensional physical model for \(V_{th}\) variations considering the combined effect of NBTI and RDF. IEEE Trans. Electron Devices 58(8), 2337–2346 (2011)CrossRef
4.
Zurück zum Zitat Wang, Y., Enachescu, M., Cotofana, S.D., Fang, L.: Variation tolerant on-chip degradation sensors for dynamic reliability management systems. Microelectron. Reliab. 52(9), 1787–1791 (2012)CrossRef Wang, Y., Enachescu, M., Cotofana, S.D., Fang, L.: Variation tolerant on-chip degradation sensors for dynamic reliability management systems. Microelectron. Reliab. 52(9), 1787–1791 (2012)CrossRef
5.
Zurück zum Zitat Schroder, D.K.: Negative bias temperature instability: what do we understand? Microelectron. Reliab. 47(6), 841–852 (2007)CrossRef Schroder, D.K.: Negative bias temperature instability: what do we understand? Microelectron. Reliab. 47(6), 841–852 (2007)CrossRef
6.
Zurück zum Zitat Singh, P., Karl, E., Blaauw, D., Sylvester, D.: Compact degradation sensors for monitoring NBTI and oxide degradation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(9), 1645–1655 (2012)CrossRef Singh, P., Karl, E., Blaauw, D., Sylvester, D.: Compact degradation sensors for monitoring NBTI and oxide degradation. IEEE Trans. Very Large Scale Integr. VLSI Syst. 20(9), 1645–1655 (2012)CrossRef
7.
Zurück zum Zitat Habchi, R., Salame, C., Khoury, A., Mialhe, P.: Temperature dependence of a silicon power device switching parameters. Appl. Phys. Lett. 88(15), 153503 (2006)CrossRef Habchi, R., Salame, C., Khoury, A., Mialhe, P.: Temperature dependence of a silicon power device switching parameters. Appl. Phys. Lett. 88(15), 153503 (2006)CrossRef
8.
Zurück zum Zitat Khan, S., Hamdioui, S.: Temperature impact on NBTI modeling in the framework of technology scaling. In: Proceeding 2nd HiPEAC Workshop on Design for Reliability, Pisa, Italy (2010) Khan, S., Hamdioui, S.: Temperature impact on NBTI modeling in the framework of technology scaling. In: Proceeding 2nd HiPEAC Workshop on Design for Reliability, Pisa, Italy (2010)
9.
Zurück zum Zitat Khan, S., Hamdioui, S.: Temperature dependence of NBTI induced delay. In: 16th IEEE International On-Line Testing Symposium (IOLTS), pp. 15–20 (2010) Khan, S., Hamdioui, S.: Temperature dependence of NBTI induced delay. In: 16th IEEE International On-Line Testing Symposium (IOLTS), pp. 15–20 (2010)
10.
Zurück zum Zitat Kim, K.K., Wang, W., Choi, K.: On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits. IEEE Trans. Circuits Syst. II Express Briefs 57(10), 798–802 (2010)CrossRef Kim, K.K., Wang, W., Choi, K.: On-chip aging sensor circuits for reliable nanometer MOSFET digital circuits. IEEE Trans. Circuits Syst. II Express Briefs 57(10), 798–802 (2010)CrossRef
11.
Zurück zum Zitat Yadav, N., Jain, S., Pattanaik, M., Sharma, G.: NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. In: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 122–128 (2014) Yadav, N., Jain, S., Pattanaik, M., Sharma, G.: NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique. In: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 122–128 (2014)
12.
Zurück zum Zitat Mostafa, H., Anis, M., Elmasry, M.: Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans. Circuits Syst. I Regul. Pap. 58(12), 2859–2871 (2011)MathSciNetCrossRef Mostafa, H., Anis, M., Elmasry, M.: Adaptive body bias for reducing the impacts of NBTI and process variations on 6T SRAM cells. IEEE Trans. Circuits Syst. I Regul. Pap. 58(12), 2859–2871 (2011)MathSciNetCrossRef
13.
Zurück zum Zitat Mostafa, H., Anis, M., Elmasry, M.: NBTI and process variations compensation circuits using adaptive body bias. IEEE Trans. Semicond. Manuf. 25(3), 460–467 (2012)CrossRef Mostafa, H., Anis, M., Elmasry, M.: NBTI and process variations compensation circuits using adaptive body bias. IEEE Trans. Semicond. Manuf. 25(3), 460–467 (2012)CrossRef
14.
Zurück zum Zitat Chen, S.L., Ker, M.D.: A new schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals. IEEE Trans. Circuits Syst. II Express Briefs 52(7), 361–365 (2005)CrossRef Chen, S.L., Ker, M.D.: A new schmitt trigger circuit in a 0.13-/spl mu/m 1/2.5-V CMOS process to receive 3.3-V input signals. IEEE Trans. Circuits Syst. II Express Briefs 52(7), 361–365 (2005)CrossRef
15.
Zurück zum Zitat Kang, K., Alam, M.A., Roy, K.: Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using \(I_{ddq}\). In: IEEE International Test Conference, ITC 2007, pp. 1–10 (2007) Kang, K., Alam, M.A., Roy, K.: Characterization of NBTI induced temporal performance degradation in nano-scale SRAM array using \(I_{ddq}\). In: IEEE International Test Conference, ITC 2007, pp. 1–10 (2007)
16.
Zurück zum Zitat Wang, Y., Cotofana, S.D., Fang, L.: Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. In: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 109–115 (2012) Wang, Y., Cotofana, S.D., Fang, L.: Statistical reliability analysis of NBTI impact on FinFET SRAMs and mitigation technique using independent-gate devices. In: IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), pp. 109–115 (2012)
17.
Zurück zum Zitat Wang, Y., Cotofana, S.D., Fang, L.: Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. J. Parallel Distrib. Comput. 74(6), 2521–2529 (2014)CrossRef Wang, Y., Cotofana, S.D., Fang, L.: Analysis of the impact of spatial and temporal variations on the stability of SRAM arrays and the mitigation technique using independent-gate devices. J. Parallel Distrib. Comput. 74(6), 2521–2529 (2014)CrossRef
18.
Zurück zum Zitat Traversi, G., Gaioni, L., Ratti, L., Manghisoni, M., Re, V.: Perspectives of 65 nm CMOS technologies for high performance front-end electronics. In: 21st International Workshop on Vertex Detectors, 026 (2012) Traversi, G., Gaioni, L., Ratti, L., Manghisoni, M., Re, V.: Perspectives of 65 nm CMOS technologies for high performance front-end electronics. In: 21st International Workshop on Vertex Detectors, 026 (2012)
19.
Zurück zum Zitat Kim, N.S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. computer 36(12), 68–75 (2003)CrossRef Kim, N.S., Austin, T., Baauw, D., Mudge, T., Flautner, K., Hu, J.S., Irwin, M.J., Kandemir, M., Narayanan, V.: Leakage current: Moore’s law meets static power. computer 36(12), 68–75 (2003)CrossRef
Metadaten
Titel
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits
verfasst von
Ambika Prasad Shah
Nandakishor Yadav
Santosh Kumar Vishvakarma
Copyright-Jahr
2017
Verlag
Springer Singapore
DOI
https://doi.org/10.1007/978-981-10-7470-7_44

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