Low Cost Dual-Phase Watermark for Protecting CE Devices in IoT Framework

Intellectual property (IP) core providers are increasingly aware of the need to protect their investment from either counterfeit/forgery or illegal ownership. This chapter presents a novel low cost dual phase watermarking methodology during high level synthesis (HLS) for IP core protection of vendor. Robust vendor signature is embedded in two subsequent phases of high level synthesis to form an integrated watermark. We present a dual-phase watermarking methodology that embeds a multi-variable double phase watermarking during high level synthesis for application specific IPs (application specific integrated circuits) that incurs zero delay and register overhead as well as minimal hardware overhead. The dual-phase watermarking approach yields average reduction of embedding cost of 6% (which includes average area reduction of 7% and average latency reduction of 4%) when compared to two recent HLS based watermarking approaches for application specific IPs. Additionally, the approach also achieves stronger proof of authorship compared to two recent HLS based watermarking approaches.