Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
MTZ-Fachkongress

Antriebe und Energiesysteme von morgen


Austausch von Automobil- und Energiewirtschaft

Am 14./15. Mai geht es in Chemnitz um die Mobilitätswende durch Elektro- und Wasserstofffahrzeuge.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Intelligence Digital Image Watermark Algorithm Based on Artificial Neural Networks Classifier Kapitel lesen Erstes Kapitel lesen

2014 | OriginalPaper | Buchkapitel

Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems

verfasst von : Davide Patti, Maurizio Palesi, Vincenzo Catania

Erschienen in: Modern Trends and Techniques in Computer Science

Verlag: Springer International Publishing

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

The rediscovery of VLIW architecture in the field of embedded multimedia applications introduces new challenges for computing paradigms historically oriented towards Instruction Level Parallelisms and performance optimization. In this work we perform an extensive multi-objective analysis which includes VLIW compiler as part of the configuration space, avoiding any explicit distinction between micro-architectural parameters and compilation strategies. After performing an high-level estimation of power/performance trade-offs by compiling and simulating some common application kernels, we qualitatively and quantitatively analyze of how the design space available can be greatly affected by the interaction of compiler behavior, processor-related features and memory subsystem.

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Wirtschaft"

Online-Abonnement

Mit Springer Professional "Wirtschaft" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 340 Zeitschriften

aus folgenden Fachgebieten:

  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Versicherung + Risiko




Jetzt Wissensvorsprung sichern!

Jetzt informieren
Vorheriges Kapitel Reducing Systems Implementation Failure: A conceptual Framework for the Improvement of Financial Systems Implementations within the Financial Services Industries
Nächstes Kapitel Numerical Solution of Ordinary Differential Equations Using Mathematical Software
Literatur
1.
Fisher, J.A.: Very long instruction word architectures and the ELI512. In: 10th Annual International Symposium on Computer Architecture., pp. 140–150 (1983)
2.
Fisher, J., Faraboschi, P., Young, C.: Vliw processors: once blue sky, now commonplace. Solid-State Circuits Mag IEEE 1, 10–17 (2009)CrossRef
3.
Boppu, S., Hannig, F., Teich, J.: Loop program mapping and compact code generation for programmable hardware accelerators. In: 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors (ASAP), pp. 10–17 (2013)
4.
Puppala, V.: Vliw—simd processor based scalable architecure for parallel classifier node computing. In: IEEE 3rd International Advance Computing Conference (IACC), pp. 1496–1502 (2013)
5.
Lapinskii, V., Jacome, M., Veciana, G.D.: Application-specific clustered VLIW datapaths: early exploration on a parameterized design space. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21, 889–903 (2002)CrossRef
6.
Sabena, D., Reorda, M., Sterpone, L.: On the automatic generation of optimized software-based self-test programs for vliw processors (2013)
7.
Najafi, M., Salehi, M.: Exploring the design space for area-efficient embedded vliw packet processing engine. In: 21st Iranian Conference on Electrical Engineering (ICEE), pp. 1–6 (2013)
8.
Givargis, T., Vahid, F., Henkel, J.: System-level exploration for Pareto-optimal configurations in parameterized System-on-a-Chip. IEEE Trans. Very Large Scale Integr. Syst. 10, 416–422 (2002)CrossRef
9.
Catania, V., Di Nuovo, A., Palesi, M., Patti, D., Morales, G.: An effective methodology to multi-objective design of application domain-specific embedded architectures. In: 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools (DSD ‘09), pp. 643–650 (2009)
10.
Taniguchi, I., Uchida, M., Tomiyama, H., Fukui, M., Raghavan, P., Catthoor, F.: An energy aware design space exploration for vliw agu model with fine grained power gating. In: 14th Euromicro Conference on Digital System Design (DSD), pp. 693–700 (2011)
11.
Pillai, A., Zhang, W., Yang, L.: Exploring functional unit design space of vliw processors for optimizing both performance and energy consumption. In: 21st International Conference on.Advanced Information Networking and Applications Workshops (AINAW ‘07), Vol. 1, pp. 792–797 (2007)
12.
Benini, L., Bruni, D., Chinosi, M., Silvano, C., Zaccaria, V., Zafalon, R.: A framework for modeling and estimating the energy dissipation of VLIW-based embedded systems. Design Autom. Embedded Syst. 7, 183–203 (2002)CrossRefMATH
13.
Pokam, G., Bodin, F.: Understanding the energy-delay tradeoff of ILP-based compilation techniques on a VLIW architecture. In: 11th Workshop on Compilers for Parallel Computers, Chiemsee, Germany (2004)
14.
Raghavan, P., Lambrechts, A., Absar, J., Jayapala, M., Catthoor, F., Verkest, D.: Coffee: compiler framework for energy-aware exploration. In: Stenstrm, P., Dubois, M., Katevenis, M., Gupta, R., Ungerer, T. (eds.) High Performance Embedded Architectures and Compilers. Lecture Notes in Computer Science, vol. 4917, pp. 193–208. Springer, Berlin (2008)CrossRef
15.
Ascia, G., Catania, V., Di Nuovo, A.G., Palesi, M., Patti, D.: Performance evaluation of efficient multi-objective evolutionary algorithms for design space exploration of embedded computer systems. Appl. Soft Comput. 11, 382–398 (2011)CrossRef
16.
Kathail, V., Schlansker, M.S., Rau, B.R.: HPL-PD architecture specification: Version 1.0. Technical report, Compiler and Architecture Research HP Laboratories Palo Alto HPL-93-80 (2000)
17.
Cai, G., Lim, C.H.: Architectural level power/performance optimization and dynamic power estimation. In: Cool Chips Tutorial colocated with MICRO32, pp. 90–113 (1999)
18.
Kamble, M.B., Ghose, K.: Analytical energy dissipation models for low power caches. In: IEEE International Symposium on Low Power Electronics and Design, pp. 143–148 (1997)
19.
Shiue, W.T., Chakrabarti, C.: Memory exploration for low power, embedded systems. In: 36th ACM/IEEE Conference on Design Automation Conference, New Orleans, Louisiana, United States, pp. 140–145 (1999)
20.
Henkel, J., Lekatsas, H.: \(a^{2} bc\): adaptive address bus coding for low power deep sub-micron designs. In: ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, pp. 744–749 (2001)
21.
Ascia, G., Catania, V., Palesi, M., Patti, D.: EPIC-explorer: a parameterized VLIW-based platform framework for design space exploration. In: First Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia), Newport Beach, California, USA, pp. 65–72 (2003)
Metadaten
Titel
Merging Compilation and Microarchitectural Configuration Spaces for Performance/Power Optimization in VLIW-Based Systems
verfasst von
Davide Patti
Maurizio Palesi
Vincenzo Catania
Copyright-Jahr
2014
Buch
Modern Trends and Techniques in Computer Science

Print ISBN: 978-3-319-06739-1

Electronic ISBN: 978-3-319-06740-7

Copyright-Jahr: 2014

DOI
https://doi.org/10.1007/978-3-319-06740-7_18

Premium Partner

    Bildnachweise