Skip to main content
Fachgebiete
Automobil + Motoren Bauwesen + Immobilien Business IT + Informatik Elektrotechnik + Elektronik Energie + Nachhaltigkeit Finance + Banking Management + Führung Marketing + Vertrieb Maschinenbau + Werkstoffe Versicherung + Risiko
DE
EN
Themenseiten
Organisationspsychologie Projektmanagement Marketing Smart Manufacturing
Bücher
Zeitschriften
Weitere Formate
Podcasts Webinare Technik Webinare Wirtschaft Kongresse Veranstaltungskalender Awards
Jetzt Einzelzugang starten
Zugang für Unternehmen
Referenzkunden
MTZ-Fachkongress

Antriebe und Energiesysteme von morgen


Austausch von Automobil- und Energiewirtschaft

Am 14./15. Mai geht es in Chemnitz um die Mobilitätswende durch Elektro- und Wasserstofffahrzeuge.
Erweiterte Suche
Anmelden
nach oben
Erschienen in:
Buchtitelbild

2011 | OriginalPaper | Buchkapitel

5. Modeling of Temporal Reliability Degradation

verfasst von : Yu Cao

Erschienen in: Predictive Technology Model for Robust Nanoelectronic Design

Verlag: Springer US

Einloggen

Aktivieren Sie unsere intelligente Suche, um passende Fachinhalte oder Patente zu finden.

search-config
loading …

Abstract

Transistor performance not only depends on static process variations, but also changes over the period of dynamic operation because of the effect of temporal reliability degradation (i.e., aging effect) [1–5]. As CMOS technology is scaling to the 10 nm regime, equivalent oxide thickness will be as thin as 5 Å [1]. Such an aggressive pace inevitably leads to multiple reliability concerns, such as negative-bias-temperature-instability (NBTI), channel-hot-carrier (CHC), and time-dependent-dielectric-breakdown (TDDB). In particular, there has been a recent increase in interest on the reliability impact of PMOS NBTI, and NMOS positive-bias temperature instability (PBTI), which is similar to NBTI and becomes pronounced after high-k gate dielectric is adopted [1, 6–9].

Sie haben noch keine Lizenz? Dann Informieren Sie sich jetzt über unsere Produkte:

Springer Professional "Wirtschaft+Technik"

Online-Abonnement

Mit Springer Professional "Wirtschaft+Technik" erhalten Sie Zugriff auf:

  • über 102.000 Bücher
  • über 537 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Finance + Banking
  • Management + Führung
  • Marketing + Vertrieb
  • Maschinenbau + Werkstoffe
  • Versicherung + Risiko

Jetzt Wissensvorsprung sichern!

Jetzt informieren

Springer Professional "Technik"

Online-Abonnement

Mit Springer Professional "Technik" erhalten Sie Zugriff auf:

  • über 67.000 Bücher
  • über 390 Zeitschriften

aus folgenden Fachgebieten:

  • Automobil + Motoren
  • Bauwesen + Immobilien
  • Business IT + Informatik
  • Elektrotechnik + Elektronik
  • Energie + Nachhaltigkeit
  • Maschinenbau + Werkstoffe




 

Jetzt Wissensvorsprung sichern!

Jetzt informieren
Literatur
1.
2.
S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De, “Parameter variations and impact on circuits and microarchitecture,” ACM/IEEE Design Automation Conference, pp. 338–342, June 2003.
3.
W. Wang, S. Yang, S. Bhardwaj, R. Vattikonda, F. Liu, S. Vrudhula, Y. Cao, “The impact of NBTI on the performance of combinational and sequential circuits,” Design Automation Conference, pp. 364–369, 2007.
4.
R. Vattikonda, W. Wang, Y. Cao, “Modeling and minimization of PMOS NBTI effect for robust nanometer design,” Design Automation Conference, pp. 1047–1052, 2006.
5.
D. K. Schroder, J. A. Babcock, “Negative bias temperature instability: road to cross in deep submicron silicon semiconductor manufacturing,” J. of Applied Physics, vol. 94, no. 1, pp. 1–17, July 2003.CrossRef
6.
N. Kimizuka, T. Yamamoto, T. Mogami, K. Yamaguchi, K. Imai, and T. Horiuchi, “The impact of bias temperature instability for direct-tunneling ultra-thin gate oxide on MOSFET scaling,” VLSI Symp. on Tech., pp. 73–74, 1999.
7.
V. Reddy, et al., “Impact of negative bias temperature instability on digital circuit reliability,” IRPS, pp. 248–254, 2002.
8.
B. C. Paul, K. Kang, H. Kufluoglu, M. A. Alam, and K. Roy, “Impact of NBTI on the temporal performance degradation of digital circuits,” EDL, vol. 26, pp. 560–562, 2003.CrossRef
9.
H. Puchner and L. Hinh, “NBTI reliability analysis for a 90 nm CMOS technology,” ESSDERC, pp. 257–260, 2004.
10.
W. Wang, V. Reddy, A. T. Krishnan, R. Vattikonda, S. Krishnan, Y. Cao, “Compact modeling and simulation of circuit reliability for 65 nm CMOS technology,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, pp. 509–517, December 2007.CrossRef
11.
A. S. Goda, G. Kapila, “Design for degradation: CAD tools for managing transistor degradation mechanisms,” ISQED, pp. 416–420, 2005.
12.
C. Hu, S. C. Tam, F.-C. Hsu, P.-K. Ko, T.-Y. Chan, and K. W. Terrill, “Hot electron induced MOSFET degradation – model, monitor, and improvement,” IEEE Tran. on Electron Devices, vol. 32, no. 2, pp. 375–385, Feb. 1985.CrossRef
13.
K. O. Jeppson and C. M. Svensson, “Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices,” J. of Applied Physics, vol. 48, pp. 2004–2014, 1977.CrossRef
14.
M. A. Alam, S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronics Reliability, vol. 45, pp. 71–81, 2005.CrossRef
15.
S. Chakravarthi, A. T. Krishnan, V. Reddy, C. F. Machala and S. Krishnan, “A comprehensive framework for predictive modeling of negative bias temperature instability,” IRPS, pp. 273–282, 2004.
16.
S. Ogawa and N. Shiono, “Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface,” Physical Review B, vol. 51, no. 7, pp. 4218–4230, February 1995.CrossRef
17.
S. Bhardwaj, W. Wang, R. Vattikonda, Y. Cao, S. Vrudhula, “A scalable model for predicting the effect of NBTI for reliable design,” IET Circuits, Devices & Systems., vol. 2, no. 4, pp. 361–371, 2008.CrossRef
18.
S. Mahapatra, D. Saha, D. Varghese, and P. B. Kumar, “On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress,” IEEE Trans. Electron Devices, vol. 53, no. 7, pp. 1583–1592, Jul. 2006.CrossRef
19.
S. Mahapatra, “Electrical characterization and modeling of negative bias temperature instability in p-MOSFET devices,” IRPS, 2006.
20.
F. C. Hsu and S. Tam, “Relationship between MOSFET degradation and hot-electron-induced interface state generation,” IEEE Electron Device Lett., vol. EDL-5, no. 2, pp. 50–52, Feb. 1984.CrossRef
21.
S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surfaces,” IEEE Trans. Electron Devices, vol. ED-27, no. 8, pp. 1497–1508, Aug. 1980.CrossRef
22.
“BSIM4 Manual,” University of California, Berkeley, 2005.
23.
S. Rangan, N. Mielke, E. C. C. Yeh, “Universal recovery behavior of negative bias temperature instability,” IEDM, pp. 341–344, 2003.
24.
A. T. Krishnan, C. Chancellor, S. Chakravarthi, P. E. Nicollian, V. Reddy, and A. Varghese, “Material dependence of hydrogen diffusion: Implication for NBTI degradation,” IEDM, 2005.
25.
G. Chen, et al., “Dynamic NBTI of PMOS transistors and its impact on device lifetime,” IRPS, pp. 196–202, 2003.
26.
V. Huard, M. Denais, “Hole trapping effect on methodology for DC and AC negative bias temperature instability measurements in PMOS transistors,” IRPS, pp. 40–45, 2004.
27.
M. A. Alam, “A critical examination of the mechanics of dynamic NBTI for PMOSFETs,” IEDM, pp. 345–348, 2003.
28.
B. Zhu, J. S. Suehle, J. B. Bernstein, and Y. Chen, “Mechanism of dynamic NBTI of pMOSFETs,” IRW, pp. 113–117, 2004.
29.
W. Zhao and Y. Cao, “New generation of Predictive Technology Model for sub-45 nm design exploration,” ISQED, pp. 585–590, 2006.
30.
R. Zheng, J. Velamala, V. Reddy, V. Balakrishnan, E. Mintarno, S. Mitra, S. Krishnan, Y. Cao, “Circuit aging prediction for low-power operation,” Custom Integrated Circuits Conference, pp. 427–430, 2009
31.
W. Wang, V. Reddy, B. Yang, V. Balakrishnan, S. Krishnan, Y. Cao, “Statistical prediction of circuit aging under process variations,” Custom Integrated Circuits Conference, pp. 13–16, 2008.
32.
S. E. Rauch, “The statistics of NBTI induced vt and β mismatch shifts in PMOSFETs,” IEEE Trans. on Device Material Reliability, pp. 89–93, 2002.
33.
S. E. Rauch, “Review and reexamination of reliability effects related to NBTI-induced statistical variations,” IEEE Transactions on Device and Materials Reliability, vol. 7, no. 4, pp. 524–530, 2007.CrossRef
34.
G. L. Rosa, W. L. Ng, S. Rauch, R. Wong, and J. Sudijono, “Impact of NBTI induced statistical variation to SRAM cell stability,” IEEE International Reliability Physics Symposium, pp. 274–282, Mar. 2006.
35.
K. Kang, S. P. Park, K. Roy, and M. A. Alam, “Estimation of statistical variation in temporal NBTI degradation and its impact on lifetime circuit performance,” IEEE/ACM International Conference on Computer-Aided Design, pp. 730–734, Nov. 2007.
36.
W. Zhao, F. Liu, K. Agarwal, D. Acharyya, S. R. Nassif, K. Nowka, Y. Cao, “Rigorous extraction of process variations for 65 nm CMOS design,” IEEE Transactions on Semiconductor Manufacturing, vol. 22, no. 1, pp. 196–203, February 2009.CrossRef
37.
Y. Cao, J. Tschanz, P. Bose, “Reliability challenges in nano-CMOS design,” IEEE Design & Test of Computers, Special Issue on Design for Reliability at 32nm and Beyond, vol. 26, no. 6, pp. 6–7, November/December 2009.
Metadaten
Titel
Modeling of Temporal Reliability Degradation
verfasst von
Yu Cao
Copyright-Jahr
2011
Verlag
Springer US
Buch
Predictive Technology Model for Robust Nanoelectronic Design

Print ISBN: 978-1-4614-0444-6

Electronic ISBN: 978-1-4614-0445-3

Copyright-Jahr: 2011

DOI
https://doi.org/10.1007/978-1-4614-0445-3_5

Neuer Inhalt

    Bildnachweise