Nanoscale VLSI

In this chapter, we review the challenges and effective design techniques for ultra-low-power analog integrated circuits. With the miniaturization, having low-power low-voltage mixed signal IC is essential to maintain the electric field in the device. This constraint presents bottleneck for the researchers to design robust analog circuits. Specifically, the low value of supply voltage with small technology influences many specifications of analog IC, e.g., power supply rejection, dynamic range and immunity to noise, etc. In addition, it also affects the ability of the MOS transistor to be operated in the strong inversion region. Note that with the technology reduction, power supply \(\textit{V}_\mathrm{DD}\) is reducing but the threshold voltage \(\textit{V}_\mathrm{T}\) is not decreasing proportionally to maintain low leakage current. However, this process reduces the overdrive voltage and limits the staking of transistors. In this case, the transistor can be made to work in weak inversion to work and reduce the power consumption. Further, reduction in \(\textit{V}_\mathrm{DD}\) to achieve low-power consumption causes many other circuit-related issues such as PVT variations, degradation of dynamic range, mismatching in circuits element and differential paths. There have been many design methods developed for the ultra-low-power analog ICs. In this chapter, we will discuss some of the design techniques to reduce the power consumption in analog ICs. In addition, we will also discuss the basic building blocks of analog circuits with discussed design techniques.

For extreme low-frequency (ELF) and super low-frequency (SLF) applications like biomedical applications (brain wave signal processing and brain–computer interface circuits), seismic signal processing applications, submarine communication applications, ultra-low-power dissipation of the electronic circuits is the most essential criterion. With the scaling of CMOS technology in the nanoscale, the contribution of leakage power becomes very significant compared to any other sources of power dissipation like switching power, bias power, etc. Subthreshold leakage current is an important component of all sources of leakage current. In modern design methodology for ultra-low-power analog circuits, this component of leakage current has been made use of for design purpose. The physics of the MOS transistor in the subthreshold region or weak inversion region is different from that when the transistor operates in the strong inversion region. Therefore, a good understanding of this physics is important for ultra-low-power design. Compact models play significant role in modern design methodologies. This chapter briefly discusses compact model for MOS transistor operating in the weak inversion region. Inversion coefficient-based design methodology for ultra-low-power analog circuits is discussed in detail. Implementation of the design methodology is then exemplified by a complete design of operational transconductance amplifier, operating in the extreme low-frequency region. Application areas of the design methodology are also discussed.

A versatile quadrature oscillator (VQO) circuit is introduced in this chapter. The circuit comprises a fully differential second-generation current conveyor (FDCCII), three resistors and two capacitors, all of which are grounded. The proposed circuit is versatile as it simultaneously delivers the voltage-mode and current-mode outputs. The oscillator circuit is benefitted with appropriately suited modern integrated circuit (IC) technology attributes such as: availability of two quadrature voltages and two quadrature currents simultaneously, orthogonal controllability of oscillation frequency as well as condition of oscillation (CO), low power consumption, low total harmonic distortion (THD), good sensitivity performance, and use of all grounded components. The proposed oscillator structure operates at ±0.9 V and hence suitable for low-voltage applications. Effects of device non-idealities and parasitic on the performance of the proposed oscillator are further analyzed. Validation of theoretical aspects of the proposed oscillator circuit is done by carrying out HSPICE simulations using 0.18 µm TSMC CMOS parameters. Furthermore, to exploit the practicality of the proposed VQO, results of experimental verification performed by connecting discrete passive components and commercially available ICs (AD844) on a breadboard are also included.

It is essential to retain power and energy efficiency in low-power integrated circuits (ICs) over a wide load current/voltage range to reduce the consumption from the battery in portable/non-portable devices. The power/energy efficiency highly depends on voltage and frequency scaling when all the parts of the devices are in operation. There are also power and clock gating when all the parts of the devices are not in operation. The dynamic and static voltage scaling are main part for power gating. The power saving can be done by varying the supply voltage to ICs. The pulse width, pulse skip, depth and frequency modulation are common techniques for clock gating/frequency generation. The pulse width modulation (PWM) is generally used for fixed frequency operation. The pulse frequency modulation (PFM) is generally used for variable frequency operation depending on load voltage and current demands. The pulse skip modulation (PSM) is special technique to skip the pulses for frequency operation depending on IC operation mode (sleep mode and standby mode). In this chapter, all the existing techniques available for power reduction are discussed with the suitable diagram and examples.

In the electronics industry, silicon is the primary material of choice to meet the demands. The advancement in the technology led to the involvement of the smaller devices with improved performance. Due to the scaling of silicon MOSFET devices, the complications increases such as tunneling effect, gate oxide leakage, and channel punch through. In order to overcome these issues, new materials with improved characteristics are needed. From the last two decades, researchers are focused to find new nanomaterials which can substitute for renowned silicon in next-generation electronic devices. Graphene is the most promising material that can replace the silicon-based materials because of its outstanding physical and electrical properties. Graphene provides high carrier velocity and high carrier concentration, resulting in large carrier mobility and faster switching capability. Moreover, graphene is a semimetal with a zero bandgap which is the basic requirement for digital integrated circuits. The quantum confinement of graphene sheet in the form of one-dimensional strips known as graphene nanoribbon (GNR). The GNR provides the energy bandgap of several hundred meV that will be helpful for the design of GNR transistor. Considering the ongoing developments in the fabrication of graphene nanoribbon (GNR) with smooth edges, the design of GNR transistor came to exist. The GNR transistors offer high ON/OFF ratios due to small carrier effective mass and direct energy gap. In this chapter, the bilayer graphene nanoribbon tunnel field-effect transistor (BL-GNRTFET) as the low-power device is discussed. Initially, the device performance which includes the study of BL-GNRTFET along with the monolayer graphene nanoribbon tunnel field-effect transistor (ML-GNRTFET) is analyzed. The parameters such as transfer characteristics, drain characteristics and transconductance are explored and compared with the ML-GNRTFET. It has been observed that the performance of the BL-GNRTFET has the better ON current, low sub-threshold swing when compared to the ML-GNRTFET.

An analytical threshold voltage model for SiGe source/drain silicon-nanotube junctionless field-effect transistor, based on the evanescent-mode analysis, is introduced. With the solution of three-dimensional Poisson equation in cylindrical coordinates, the surface potential along the channel length is determined with suitable boundary conditions. Using these models, the impact of physical device parameters such as core gate radius, oxide thickness, and nanotube thickness on the threshold voltage behavior and drain-induced barrier lowering has been studied. It is shown through extensive analysis that the proposed analytical models are in excellent agreement with TCAD numerical simulation results.

The III-V compound semiconductor-based quantum-well field-effect transistor (QWFET) is one of the most promising solid-state transistor technologies for future high-speed, low-power logic integrated circuit applications due to their high speed and low-voltage operation. This excellent speed and low voltage operation mainly comes from the unique properties of III-V compound semiconductors such as high electron and hole mobility, high electron velocity saturation and high sheet carrier concentration, etc. High-performance III-V compound semiconductor-based n-channel QWFETs are widely available. But, for implementing high-speed low-power CMOS logic integrated circuits, there is a critical issue of identifying high-performance III-V compound semiconductor -based p-channel quantum-well transistors. In order to fully utilize the potential of high mobility III-V compound semiconductor channel materials, instead of developing large diameter III-V wafers, it is better to couple III-V transistors with traditional silicon wafers. This chapter deals with the architecture and electrical performance of III-V nanoscale quantum-well field-effect transistors for future high-speed and low-power logic integrated circuit applications.

Aggressive scaling of metal–oxide–semiconductor field-effect transistor (MOSFET) is a barrier in the progress of very large-scale integration (VLSI) technology, and new innovative devices and techniques are always required to boost the electronics industry. Fin-shaped field-effect transistor (FinFET) is the appropriate device to eliminate the limitations of MOSFET devices. FinFET is a three-dimensional (3D) multi-gate transistor with improved channel stability, less short channel effects (SCEs) and excellent isolation compared to the MOS transistor. The best qualities of FinFET that attracts research designers are better SCEs, improved subthreshold slope, less random doping fluctuation and independent gating. Process, voltage and temperature (PVT) variation is one of the scaling problems in MOSFET devices, and due to PVT variations, the circuit shows abnormal power consumption and performance degradation. In this chapter, we concentrate on the influence of PVT variations on different FinFET-based circuits. PVT variations can cause deviation in power consumption, delay and leakage current which finally degrade the performance of FinFET devices.

The development of the silicon (Si)-based deep submicron devices has promised significant improvement in the quality of life, including new technologies for the treatment of diseases and greater efficiency for storing and processing the computer data. It is a well-known fact that electronics industry has undoubtedly benefited from the Si-based technology that uses much lower power and offers cost-effective circuits and devices due to mass fabrication. But is it feasible for Si technology to improve and revive the electronics industry, speed up its growth, and enable rapid development of portable and compact products? An additional aspect which needs to be established is the choice of the right innovative materials and devices that will allow the electronics industry to grow and develop new low-power systems, along with the possible potential of renovating this industry. Various researchers throughout the world are evaluating distinct and effective methodologies to solve this problem, and gallium nitride (GaN) technology has come out as one of the major breakthroughs and innovations. This chapter mainly focuses on the basics of advanced materials beyond Si and germanium (Ge) which can be used for the fabrication of various electronic devices such as transistors, gates, oscillators, and amplifiers. It addresses the advantages and disadvantages associated with the usage of these materials for modern electronic devices and low-power VLSI circuits.

In analog and digital circuit, voltage controlled oscillator (VCO) plays a very important role in electronic circuits such as phase locked loop (PLL), radio frequency integrated circuits (RFICs), analog to digital converter (ADC) and other circuits. (Sun and KwasniewskI in IEEE J Solid State Circuits 36:910–916, 2001; Razavi in IEEE J Solid State Circuits 32:730–735, 1997; Jovanovic and Stojcev in Int J Electron 93:167–175, 2006; Hajimiri et al. in IEEE J Solid State Circuits 34:790–804, 1999; Jovanovic et al. in Sci Publ State Univ Novi Pazar 2:1–9, 2010). The VCO is an electronic circuit, which produces the frequency signal depending on its input voltage. VCO is voltage to frequency converter. VCO provides a better linear relationship among the variable control voltage and tuning oscillation frequency, which is a concern in many applications. In ring oscillator, the number of stages in the standard structure indicates the multiphase output in broad operating frequency (Jovanovic et al. in Sci Publ State Univ Novi Pazar 2:1–9, 2010). In this chapter, we have focused on the designing of stable frequency and low-power hybrid VS-CNTFET-CMOS VCO ring oscillator, which generate better linearity as compared to conventional CMOS design. Due to higher electron mobility and excellent transportation of career of CNTFET, it is used in many analog and radio frequency (RF frequency) (Yang et al. in Appl Phys Lett 88:113507, 2006; Appenzeller et al. in 1:184–189, 2002; Akinwande et al. in IEEE Trans Nanotechnol 7(5):636–639, 2008; Cho et al. in MTL Annu Res Rep, 2007; Chakraborty et al. in IEEE TransCircuits Syst IRegul Pap 54(11):2480–2488, 2007). Recently, CNTFETs are a most popular device for RF applications. A chemical sensing application utilizing hybrid CMOS-CNTFET approach is reported in (Rahane and Kureshi in Int J Appl Eng Res 12:1969–1973, 2017). A low power and linear voltage controlled oscillator using hybrid CMOS-CNFET is used for RF application (Rahane and Kureshi in Int J Appl Eng Res 12:1969–1973, 2017). In this chapter, we designed five-stage “Hybrid VS-CNEFT-CMOS RVCO using Current Starved Power Switching Technology”. The design VCO operates at the low supply voltage. This design does not only increase the frequency and current but also reduces the power dissipation and RMS jitter. We have used P-CNTFET and N-CNTFET in the place of convention PMOS and NMOS, respectively, which have small switching time, less threshold voltage (V_th) and less power consumption.

Interconnects are the basic connections used to establish between two silicon-based chips or devices. Basically, the interconnect quality and size differ based on the physics on which these work, such as electrical and/or optical. With the increased demand of the high quality and speedup communication, it is essential to work on the various different aspects of the chip. Conventional interconnects used in electronics devices are basically electrical, and these are reaching to their limits. Since Moor’s law suggests that the density of electrical component gets double in every 18 months, but with the increasing density of the components on/off chip, it is not possible to scale interconnect beyond a particular limit. Optical interconnects are feasible option which overcome the delay, loss, parasitic capacitance, etc., of electrical interconnect. In optical interconnects, nonlinear signals are transmitted through silicon-based waveguide through either two-dimensional or three-dimensional fabrication. Progression in nanotechnology made it viable to arrange light source; laser, medium; waveguide, and detector; and photodiode into a single silicon chip. However, there are still a lot of challenges to commercially implement dense optical interconnects to silicon chips, such as losses, packaging, and integration of two different technologies in single chip. It is observed that optical interconnect technology is not mature enough and needs a thorough analysis. On the designing aspect, there are a lot of features of optical interconnects which need to be addressed. Thus, this chapter is focused on optical interconnects for silicon on insulator (SOI) chips, analyzed the work which is already done and the basic challenges in this technology to make it practical.

Electronic devices are the basic building blocks in integrated circuits. Silicon-based devices are dominating the VLSI industry since decades. However, with miniaturization of the technology, quantum effects aggregate extensively at nano-dimensions, and silicon-based devices are harder to scale down than tens of nanometer. As a result, traditional silicon FETs at nano-era are becoming less significant. The rise of nano-era and recent research trends have shown that graphene and related materials (GRMs) are emerging as promising candidates for future devices. In this chapter, the physics governing the graphene material is discussed. Thereafter, analytical model of graphene FET (GFET) is presented. Further, advanced GFET is explored, and the high end novel GFET-based inverter and adder circuits are implemented using HSPICE. To investigate the GFET performance efficiency, a comparative analysis has also been made with respect to conventional SiFET devices. The technology node considered for SiFET is 22 nm for the various analyses presented in the chapter.

Magnetic quantum-dot cellular automata (MQCA)-based nanomagnetic logic computation started emerging to augment the CMOS-based traditional computing devices as Moore’s law approaching towards its end. Computation performed using nanomagnets exhibits non-volatility and adheres to the thermodynamic law (second). The emerging advents in the field of artificial intelligence computing on edge with the constrained resources necessitate rebooting the computing paradigm beyond CMOS and more than Moore to cater for area and power efficiency. In this regard, digital logic arithmetic circuits should be revisited using this energy-efficient computing paradigm using nanomagnets. This chapter summarizes the undergoing research in the design of such arithmetic architecture development and its corresponding nanomagnetic implementation. Researchers have demonstrated the MQCA-based arithmetic architecture implementation using inplane nanomagnetic logic (iNML) utilizing the dipole coupling. Design methodologies presented in the literatures have exploited the shape (S), positional (P), shape & positional-based hybrid nanomagnetic anisotropies pertaining to the optimization in terms of required number of resources in terms of nanomagnets (NMs), clock cycles (CCs) and majority gates (MGs) which are the critical constraints leading to high speed, area and energy-efficient design. Subsequently, researchers have exploited physical analogy of the basic building block, i.e. the three inputs nanomagnetic majority logic gate for enhanced optimization in the nanomagnetic design. However, for higher integration densities and efficient area consumption, the scalability of the dipole coupling-based nanomagnetic devices is an important aspect which is eventually limited by its susceptibility to thermal fluctuations. In this regard, interlayer exchange-coupled (IEC) scheme has been demonstrated and has been shown to offer stronger interaction between thin nanomagnets, resulting in greater scalability and better data retention at the deep sub-micron level, hence allowing magnetic interaction to be manipulated both in the vertical and lateral directions at the same time. In this regard, interlayer exchange-coupling scheme has been discussed as a possible solution to better scalability and data retention. Interlayer exchange-coupled system comprises of a non-magnetic metal layer (known as spacer layer) sandwiched between two ferromagnetic layers. The two ferromagnetic layers may be coupled ferromagnetically (FM) or antiferromagnetically (AFM), decided by the thickness and material (e.g. chromium, copper, ruthenium) of the spacer layer. On the other hand, perpendicular Nanomagnetic Logic (pNML) has involved a lot of interest for 3D architecture exploration. This chapter gives an overview on the emerging nanoscale architecture circuits, design and its implementation using nanomagnets. The implementation of nanomagnetic logic for data transmission in 3D IC has also been discussed, resulting in higher packing densities in 3D IC’s.

Digital signal processing (DSP) hardware is ubiquitous in the current generation of consumer electronics systems including camera, camcorders, set-top boxes, smartphones, etc. The very large-scale integration (VLSI) design process of DSP hardware is entirely dependent on high-level synthesis framework that comprises design space exploration (DSE) of power/area-delay trade-off. Since DSP hardware is application specific by nature, and thus, exploration of its low power, high performance architectural solution is crucial. However, the exploration process is intricate and involves a number of convoluted factors such as modelling of the objective function (such as power and delay), accuracy/efficiency of the optimization framework, loop dependency, data pipelining, seed encoding, scheduling algorithm, resource binding, ability to escape local minima and terminating criteria. In this chapter, we present a number of emerging evolutionary design space exploration techniques based on bacterial foraging and particle swarm optimization algorithm that is capable to consider the aforesaid complex factors while performing power/area—delay trade-off of DSP hardware. The chapter also discusses the analysis on case studies for each DSE technique with respect to power–delay trade-off.

Over the years, a rapid growth has been witnessed in electronics semiconductor industry because of the huge demand for system-level designs. System-level designs are prominently used for various applications such as high-performance computing, controls, telecommunications, image and video processing, consumer electronics and others. Hence to accomplish such applications using very large-scale integration (VLSI) design, it is recommended to have an efficient register-transfer-level (RTL) design abstraction, as it can provide a low power and high-performance outcome (Wu and Liu in IEEE Trans Very Large Scale Integr (VLSI) Syst 6:707–718, Wu and Liu 1998). In digital integrated circuit (IC) design, RTL models a synchronous digital circuit in terms of the flow of digital signals or data between hardware registers and the logical operations performed on these signals. RTL abstraction is used in hardware description languages (HDLs) to create high-level representations of a circuit (Chinedu et al. in 3rd IEEE international conference on adaptive science and technology (ICAST 2011). IEEE, pp 262–267, Chinedu et al. 2011). From these lower-level representations, ultimately actual circuitry can be derived. Design at the RTL level is a typical practice in modern digital system designs. This chapter mainly focuses on design of RTLs for application-specific integrated circuits (ASICs) and how it differs for field-programmable gate arrays (FPGAs). The examples and modules discussed in this chapter are written in HDL, viz. Verilog language.