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Erschienen in:
IoT: Bird’s Eye View, Megatrends and Perspectives Kapitel lesen Erstes Kapitel lesen

2017 | OriginalPaper | Buchkapitel

4. Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing

verfasst von : Massimo Alioto

Erschienen in: Enabling the Internet of Things

Verlag: Springer International Publishing

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Abstract

This chapter addresses the challenges and the opportunities to perform computation with nearly-minimum energy consumption through the adoption of logic circuits operating at near-threshold voltages. Simple models are provided to gain an insight into the fundamental design tradeoffs. A wide set of design techniques is presented to preserve the nearly-minimum energy feature in spite of the fundamental challenges in terms of performance, leakage and variations. Emphasis is given on debunking the incorrect assumptions that stem from traditional low-power common wisdom at above-threshold voltages.

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Vorheriges Kapitel Ultra-Low-Power Digital Architectures for the Internet of Things
Nächstes Kapitel Energy Efficient Volatile Memory Circuits for the IoT Era
Fußnoten
1
Indeed, sub-100 nm CMOS technologies typically have an I–V characteristics that is proportional to \( {\left({V}_{DD}-{V}_{TH}\right)}^{\alpha} \) with \( \alpha \approx 1 \) (Sakurai and Newton 1990).
 
2
Operation at near-threshold voltages tends to increase \( {V}_{TH} \) compared to the value at nominal voltage, due to DIBL (see Sect. 5.​2.​2). For standard \( {V}_{TH} \) of 350–380 mV at nominal voltage, it is common to have \( {V}_{TH} \) in the order of 400–450 mV when operating at near-threshold voltages (see, e.g., Fig. 4.7). Observe that the “standard V TH ” nomenclature might be attributed to different threshold voltages in some processes.
 
3
Indeed, \( \ln \left({e}^x+1\right)\approx {e}^x \) for \( x<0 \) (i.e., for \( {V}_{DD}<{V}_{TH} \)) in (5.2).
 
4
These considerations hold for NMOS transistors. For PMOS transistors, change the sign in all voltages. Regarding the body effect, FBB (RBB) refers to body voltages \( {V}_{BB} \) below (above) \( {V}_{DD} \).
 
5
An operation is here defined as the basic task that the considered system is executing, e.g., an instruction in a CPU or GPU, a new output sample in a DSP, an arithmetic operation in an Arithmetic Logic Unit.
 
6
\( {T}_{CK}/ F O4 \) is essentially constant in gate-delay dominated critical paths when varying \( {V}_{DD} \), as all gate delays generally scale like \( F O4 \) (Harris et al. n.d.; Weste and Harris 2011). At near-threshold voltages, this assumption is generally correct, as the wire delay is typically much smaller (see Sect. 5.2.3).
 
7
Since the energy per operation \( {E}_{TOT} \) in (5.11) is proportional to \( {E}_{cycle} \), in the following we will simply refer to the energy per cycle in (5.12), unless otherwise specified. All considerations are immediately extended to \( {E}_{TOT} \) by simply multiplying \( {E}_{cycle} \) by \( C P O \).
 
8
The following analysis is inspired by Hanson et al. (2006a), Hanson et al. (2006b), Bo et al. (2004) and generalizes the results to arbitrary designs, instead of being valid only for simple cascaded inverters.
 
9
For example, the average fan-out \( \overline{C_{cell}}/{C}_{in, min} \) is independent of \( {V}_{DD} \) since the wire capacitance is constant, and the transistor gate capacitance does not change substantially (see Fig. 5.​4). Similarly, the logic depth, the activity and the average strength do not depend on \( {V}_{DD} \).
 
10
Indeed, eq. (5.13) in sub-threshold region becomes \( {E}_{cycle}\propto {V}_{DD, norm}^2\left[1+ ILDR\cdot {e}^{-{V}_{DD, norm}}\right] \), assuming \( {\alpha}_{X_{off}}\approx {\lambda}_{DIBL} \) (which is generally, since \( {\lambda}_{DIBL}\ll 1 \)).
 
11
Here, “fast” refers to the clock cycle normalized to \( F O4 \) (i.e., \( L{D}_{eff} \)), rather than the absolute clock cycle. This choice is motivated by the need for characterizing the design regardless of the specific voltage and hence \( F O4 \). Indeed, low values of \( {T}_{CK}/ F O4 \) identify designs that would be fast at nominal and any other voltage, regardless of \( F O4 \). On the other hand, ultra-low voltage operation makes the absolute \( {T}_{CK} \) large simply because of the increase in \( F O4 \), not because of the design itself.
 
12
The off (on) stacking factor is defined as the factor by which the transistor current of an off (on) single transistor is reduced due to the series connection of multiple transistors having the same size.
 
13
This is unavoidable in real designs, as overall energy-performance optimization aims to equalize the delay of different paths (De Micheli 1994), so that non-critical paths can be down-sized to reduce their energy, while maintaining the same performance target (Narayanan et al. 2010).
 
14
This is due to the well-known quadratic dependence of the RC wire delay on its length (Weste and Harris 2011), and assuming a 10X \( F O4 \) degradation at the MEP compared to the nominal voltage.
 
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Metadaten
Titel
Near-Threshold Digital Circuits for Nearly-Minimum Energy Processing
verfasst von
Massimo Alioto
Copyright-Jahr
2017
Buch
Enabling the Internet of Things

Print ISBN: 978-3-319-51480-2

Electronic ISBN: 978-3-319-51482-6

Copyright-Jahr: 2017

DOI
https://doi.org/10.1007/978-3-319-51482-6_4

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