New Energy Efficient Reconfigurable FIR Filter Architecture and Its VLSI Implementation

High performance and energy efficient reconfigurable FIR filter is the imperative requirement in the modern wireless communication applications. The transposed form block FIR filter based on distributed arithmetic proves to best suit the requirements of such application. Therefore, this paper presents a new energy efficient, multiplier-less transposed form block FIR filter architecture for reconfigurable applications using distributed arithmetic based approach. The proposed architecture provides improved area-delay product (ADP) and reconfigurability by employing efficient coefficient storage unit and multiplication using add-and-shift logic, respectively. The synthesis results at FPGA level show that the proposed architecture exhibits 13.15% and 13.33% reduced energy per sample for the filter length 64 with a block size of 4 and 8 samples respectively, over the existing design. Further, ASIC level results for filter length 64 and block size 8 shows 20.91% reduction in ADP and 32.86% reduction in the area over the existing architecture.