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Erschienen in:
Introduction Kapitel lesen Erstes Kapitel lesen

2018 | OriginalPaper | Buchkapitel

5. On-Demand Fault-Tolerant Loop Processing

verfasst von : Alexandru-Petru Tanase, Frank Hannig, Jürgen Teich

Erschienen in: Symbolic Parallelization of Nested Loop Programs

Verlag: Springer International Publishing

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Abstract

Since the feature sizes of silicon devices continue to shrink, it is imperative to counter the increasing proneness to errors of modern, complex systems by applying appropriate fault tolerance measures. In this chapter, we therefore propose new techniques that leverage the advantages of self-organizing computing paradigms such as invasive computing to implement fault tolerance on multiprocessor systems-on-chips (MPSoCs) adaptively. We presented new compile time transformations that introduce modular redundancy into a loop program to protect it against soft errors. Our approach uses the abundant number of processing elements (PEs) within a tightly coupled processor array (TCPA) to claim not only one region of a processor array, but instead two (dual modular redundancy (DMR)) or three (triple modular redundancy (TMR)) contiguous neighboring regions of PEs. At the source code level, the compiler realizes these replication schemes with a program transformation that: (1) replicates a parallel loop program two or three times for DMR or TMR, respectively, and (2) introduces appropriate voting operations whose frequency and location may be chosen from three proposed variants. Which variant to choose depends, for example, on the error resilience needs of the application or the expected soft error rates. Finally, we explore the different tradeoffs of these variants regarding performance overheads and error detection latency.

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Vorheriges Kapitel Symbolic Multi-Level Parallelization
Nächstes Kapitel Conclusions and Outlook
Fußnoten
1
The tiled code is obtained using outer loop parallelization which was described in detail in Sect. 3.​1.
 
2
The non-replicated tiled processor space is denoted by the set \(\mathcal {P}=\{p\ | \ p=\Phi I \wedge I\in \mathcal {J} \oplus \mathcal {K}\}\). For more details, see the definition of the space-time mapping from Sect. 2.​3.​5.
 
3
Note that π may be often chosen smaller than the latency of one loop iteration. In that case, the execution of multiple iterations does overlap (also called modulo scheduling).
 
4
For more details on how a latency of two cycles for a voting operation is obtained, we refer to Sect. 5.3.
 
5
The original iteration interval π = 1 increases by two cycles due to voting operation.
 
6
Assuming sufficient FUs are available, so that the computations are not delayed unnecessarily due to resource limitations.
 
7
Safety Integrity Levels are defined based on the Probability of Failure per Hour (PFH), namely, SIL 1: PFH = 10−5…10−6; SIL 2: PFH = 10−6…10−7; SIL 3: PFH = 10−7…10−8; SIL 4: PFH = 10−8…10−9.
 
8
A module is assumed here to be a full Processing Element (PE).
 
9
In terms of the latency L, we computed latency-optimal linear schedules for each case.
 
10
One cycle for performing a comparison and one for branching, see the code presented in Sect. 5.3.
 
11
Input data must be provided as a copy to the border PEs of each replica. Also, only voted output data must be selected and stored outside the array. For details, we refer to [HSL+13, SHT15].
 
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Metadaten
Titel
On-Demand Fault-Tolerant Loop Processing
verfasst von
Alexandru-Petru Tanase
Frank Hannig
Jürgen Teich
Copyright-Jahr
2018
Buch
Symbolic Parallelization of Nested Loop Programs

Print ISBN: 978-3-319-73908-3

Electronic ISBN: 978-3-319-73909-0

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-3-319-73909-0_5

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