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Erschienen in:
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2018 | OriginalPaper | Buchkapitel

Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits

verfasst von : Inamul Hussain, Saurabh Chaudhury

Erschienen in: Advances in Communication, Devices and Networking

Verlag: Springer Singapore

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Abstract

Adders are the integral part of arithmetic logic units in digital system. Performance of the adder circuits decides the performance of those circuit and systems. Full adders are designed either in conventional approach or hybrid approach. In conventional approach, only one logic style is used, whereas in hybrid approach, two or more logic styles are used. A performance analysis between conventional and hybrid 1-bit full adder circuits is presented in this paper. In conventional design, complementary metal–oxide–semiconductor (CMOS) full adder, complementary pass logic (CPL) full adder, and transmission gate full adder (TGA) are the most popular. In this paper, CMOS full adder and CPL full adder are reported. The hybrid adder reported in this paper is designed using CMOS logic and transmission gate (TG) logic. The circuits are implemented using Cadence virtuoso tools with 180 nm United Microelectronics Company (UMC) technology. From the pre-layout simulation, performance metrics such as power, speed, and power delay products were computed. Performance of each of the circuits in terms of power, speed, power delay product (PDP), and area requirements in terms of transistor counts for the design is then compared.

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Vorheriges Kapitel Design of an Energy Efficient, Low Phase Noise Current-Starved VCO Using Pseudo-NMOS Logic
Nächstes Kapitel VLSI Implementation of Booth’s Multiplier Using Different Adders
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Metadaten
Titel
Performance Comparison of 1-Bit Conventional and Hybrid Full Adder Circuits
verfasst von
Inamul Hussain
Saurabh Chaudhury
Copyright-Jahr
2018
Verlag
Springer Singapore
Buch
Advances in Communication, Devices and Networking

Print ISBN: 978-981-10-7900-9

Electronic ISBN: 978-981-10-7901-6

Copyright-Jahr: 2018

DOI
https://doi.org/10.1007/978-981-10-7901-6_6

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