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2018 | OriginalPaper | Buchkapitel

Performance Sensor for Reliable Operation

verfasst von : Jorge Semião, Ruben Cabral, Marcelino B. Santos, Isabel C. Teixeira, J. Paulo Teixeira

Erschienen in: Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments

Verlag: Springer International Publishing

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Abstract

Human-Computer Interaction (HCI) applications need reliable hardware and the development of today’s sensors and cyber-physical systems for HCI applications is critical. Moreover, such hardware is becoming more and more self-powered, and mobile devices are today important devices for HCI applications. While battery-operated devices quest for the never-ending battery, aggressive low-power techniques are used in today’s hardware systems to accomplish such mission. Techniques like Dynamic Voltage and Frequency Scaling (DVFS) and the use of subthreshold power-supply voltages can effectively achieve substantial power savings. However, working at reduced power-supply voltages, and reduced clock frequency, imposes additional challenges in the design and operation of devices. Today’s chips face several parametric variations, such as PVTA (Process, power-supply Voltage, Temperature and Aging) variation, which can affect circuit performance and reliability is affected. This paper presents a performance sensor solution to be used in cyber-physical systems to improve reliability of today’s chips, guaranteeing an error-free operation, even with the use of aggressive low-power techniques. In fact, this performance sensor allows optimize the trade-off between power and performance, avoiding the occurrence of errors. In order to be easily used and adopted by industry, the performance sensor is a non-intrusive global sensor, which uses two dummy critical paths to sense performance for the power-supply voltage and clock frequency used, and for the existing PVTA variation. The novelty of this solution is on the new architecture for the sensor, which allows the operation at VDDs’ subthreshold voltage levels. This feature makes this global sensor a unique solution to control DVFS, even at subthreshold voltages, avoid performance errors and allow optimizing circuit operation and performance. Simulations using a SPICE tool allowed characterizing the new sensor to work at sub-threshold voltages, and results are presented for a 65 nm CMOS technology, which uses a CMOS Predictive Technology Models (PTM) technology. The results show that the sensor increases sensibility when PVTA degradations increase, even when working at subthreshold voltages.

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Literatur
1.
2.
Zurück zum Zitat Yoo, H.J.: Dual vt self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM. IEEE Trans. Circ. Syst. II Analog Digit. Sig. Process. 45(9), 1263–1271 (1998)CrossRef Yoo, H.J.: Dual vt self-timed CMOS logic for low subthreshold current multigigabit synchronous DRAM. IEEE Trans. Circ. Syst. II Analog Digit. Sig. Process. 45(9), 1263–1271 (1998)CrossRef
3.
Zurück zum Zitat Hanson, S., Seok, M., Sylvester, D., Blaauw, D.: Nanometer device scaling in subthreshold logic and SRAM. IEEE Trans. Electron Devices 55, 175–185 (2008)CrossRef Hanson, S., Seok, M., Sylvester, D., Blaauw, D.: Nanometer device scaling in subthreshold logic and SRAM. IEEE Trans. Electron Devices 55, 175–185 (2008)CrossRef
4.
Zurück zum Zitat Chakraborty, S., Mallik, A., Sarkar, C.K.: Subthreshold performance of dual-material gate CMOS devices and circuits for ultra-low power analog/mixed-signal applications. IEEE Trans. Electron Devices 55(3), 827–832 (2008)CrossRef Chakraborty, S., Mallik, A., Sarkar, C.K.: Subthreshold performance of dual-material gate CMOS devices and circuits for ultra-low power analog/mixed-signal applications. IEEE Trans. Electron Devices 55(3), 827–832 (2008)CrossRef
5.
Zurück zum Zitat Do, A.V., Boon, C.C., Anh, M., Yeo, K.S., Cabuk, A.: A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band. IEEE Trans. Microw. Theory Tech. 56(2), 286–292 (2008)CrossRef Do, A.V., Boon, C.C., Anh, M., Yeo, K.S., Cabuk, A.: A subthreshold low-noise amplifier optimized for ultra-low-power applications in the ISM band. IEEE Trans. Microw. Theory Tech. 56(2), 286–292 (2008)CrossRef
6.
Zurück zum Zitat Giustolisi, G., Palumbo, G., Criscione, M., Cutri, F.: A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J. Solid-State Circuits 38(1), 151–154 (2003)CrossRef Giustolisi, G., Palumbo, G., Criscione, M., Cutri, F.: A low-voltage low-power voltage reference based on subthreshold MOSFETs. IEEE J. Solid-State Circuits 38(1), 151–154 (2003)CrossRef
7.
Zurück zum Zitat Li, M.-Z., et al.: Sub-threshold standard cell library design for ultra-low power biomedical applications. In: 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), p. 1454 (2013) Li, M.-Z., et al.: Sub-threshold standard cell library design for ultra-low power biomedical applications. In: 2013 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), p. 1454 (2013)
8.
Zurück zum Zitat Sahu, A., Eappen, G.: Sub-threshold logic and standard cell library. Int. J. Innov. Res. Sci. Eng. Technol. 3(1) (2014) Sahu, A., Eappen, G.: Sub-threshold logic and standard cell library. Int. J. Innov. Res. Sci. Eng. Technol. 3(1) (2014)
9.
Zurück zum Zitat Martins, C.V., Semião, J., Vazquez, J.C.,Champaq, V., Santos, M., Teixeira, I.C., Teixeira, J.P.: Adaptive error-prediction flip-flop for performance failure prediction with aging sensors. In: 29th IEEE VLSI Test Symposium 2011 (VTS 2011), Dana Point, California, USA, 1st–5th May 2011 Martins, C.V., Semião, J., Vazquez, J.C.,Champaq, V., Santos, M., Teixeira, I.C., Teixeira, J.P.: Adaptive error-prediction flip-flop for performance failure prediction with aging sensors. In: 29th IEEE VLSI Test Symposium 2011 (VTS 2011), Dana Point, California, USA, 1st–5th May 2011
10.
Zurück zum Zitat Martins, C., Pachito, J., Semião, J., Teixeira, I.C., Teixeira, J.P.: Adaptive error-prediction aging sensor for on-line monitoring of performance errors. In: Proceedings of the 26th Conference on Design of Circuits and Integrated Systems – DCIS 2011, Albufeira, Portugal, 16–18 November 2011 Martins, C., Pachito, J., Semião, J., Teixeira, I.C., Teixeira, J.P.: Adaptive error-prediction aging sensor for on-line monitoring of performance errors. In: Proceedings of the 26th Conference on Design of Circuits and Integrated Systems – DCIS 2011, Albufeira, Portugal, 16–18 November 2011
11.
Zurück zum Zitat Ernst, D., Kim, N.S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., Mudge, T.: Razor: a low-power pipeline based on circuit-level timing speculation. In: 2003 Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-36, December 2003 Ernst, D., Kim, N.S., Das, S., Pant, S., Rao, R., Pham, T., Ziesler, C., Blaauw, D., Austin, T., Flautner, K., Mudge, T.: Razor: a low-power pipeline based on circuit-level timing speculation. In: 2003 Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-36, December 2003
12.
Zurück zum Zitat Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D.M., Blaauw, D.T.: RazorII: in situ error detection and correction for PVT and SER Tolerance. IEEE J. Solid-State Circuits 44(1), January 2009CrossRef Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D.M., Blaauw, D.T.: RazorII: in situ error detection and correction for PVT and SER Tolerance. IEEE J. Solid-State Circuits 44(1), January 2009CrossRef
13.
Zurück zum Zitat Semião, J., Cabral, R., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Dynamic voltage and frequency scaling for long-term and fail-safe operation. In: The Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN Finale 2015), Tallinn, Estonia, 10–11 November 2015 Semião, J., Cabral, R., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Dynamic voltage and frequency scaling for long-term and fail-safe operation. In: The Finale Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN Finale 2015), Tallinn, Estonia, 10–11 November 2015
15.
Zurück zum Zitat Semião, J., Rodriguez-Irago, M., Piccoli, L., Vargas, F., Santos, M.B., Teixeira, I.C., Rodríguez-Andina, J.J., Teixeira, J.P.: Signal integrity enhancement in digital circuits. IEEE Des. Test Comput. 25(5), 452–461 (2008)CrossRef Semião, J., Rodriguez-Irago, M., Piccoli, L., Vargas, F., Santos, M.B., Teixeira, I.C., Rodríguez-Andina, J.J., Teixeira, J.P.: Signal integrity enhancement in digital circuits. IEEE Des. Test Comput. 25(5), 452–461 (2008)CrossRef
16.
Zurück zum Zitat Agarwal, M., et al.: Circuit failure prediction and its application to transistor aging. In: Proceedings of the VLSI Test Symposium (VTS), pp. 277–286 (2007) Agarwal, M., et al.: Circuit failure prediction and its application to transistor aging. In: Proceedings of the VLSI Test Symposium (VTS), pp. 277–286 (2007)
17.
Zurück zum Zitat Vazquez, J.C., et al.: Predictive error detection by on-line aging monitoring. In: Proceedings of the IEEE International On-Line Test Symposium (IOLTS) (2010) Vazquez, J.C., et al.: Predictive error detection by on-line aging monitoring. In: Proceedings of the IEEE International On-Line Test Symposium (IOLTS) (2010)
18.
Zurück zum Zitat Blaauw, D., Kalaiselvan, S., Lai, K., Ma, W.-H., Pant, S., Tokunaga, C., Das, S., Bull, D.: Razor II: in situ error detection and correction for PVT and SER tolerance. In: Proceedings of the 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, pp. 400–622, 3–7 February 2008 Blaauw, D., Kalaiselvan, S., Lai, K., Ma, W.-H., Pant, S., Tokunaga, C., Das, S., Bull, D.: Razor II: in situ error detection and correction for PVT and SER tolerance. In: Proceedings of the 2008 IEEE International Solid-State Circuits Conference, ISSCC 2008, Digest of Technical Papers, pp. 400–622, 3–7 February 2008
20.
Zurück zum Zitat Tschanz, J., et al.: Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 292–293 (2007) Tschanz, J., et al.: Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging. In: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), pp. 292–293 (2007)
21.
Zurück zum Zitat Gauthier, C.R., Trivedi, P.R., Yee, G.S.: Embedded Integrated Circuit Aging Sensor System. Sun Microsystems, US Patent 7054787, 30 May 2006 Gauthier, C.R., Trivedi, P.R., Yee, G.S.: Embedded Integrated Circuit Aging Sensor System. Sun Microsystems, US Patent 7054787, 30 May 2006
22.
Zurück zum Zitat D. Kim, J. Kim, M. Kim, J. Moulic, H. Song, “System and Method for Monitoring Reliability of a Digital System”, IBM Corp., US Patent 7495519, 24 February 2009 D. Kim, J. Kim, M. Kim, J. Moulic, H. Song, “System and Method for Monitoring Reliability of a Digital System”, IBM Corp., US Patent 7495519, 24 February 2009
23.
Zurück zum Zitat Keane, J., Kim, T., Kim, C.: An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. In: Proceedings of the International. Symposium on Low Power Electronics and Design (ISLPED), pp. 189–194 (2007) Keane, J., Kim, T., Kim, C.: An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. In: Proceedings of the International. Symposium on Low Power Electronics and Design (ISLPED), pp. 189–194 (2007)
24.
Zurück zum Zitat Austin, T., Blaauw, D., Mudge, T., Flautner, K.: Making typical silicon matter with Razor. IEEE Comput. 37(3), 57–65 (2004)CrossRef Austin, T., Blaauw, D., Mudge, T., Flautner, K.: Making typical silicon matter with Razor. IEEE Comput. 37(3), 57–65 (2004)CrossRef
25.
Zurück zum Zitat Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D., Blaauw, D.: RazorII: in situ error detection and correction for PVT and SER tolerance. IEEE J. Solid-State Circuits 44(1), 32–48 (2009)CrossRef Das, S., Tokunaga, C., Pant, S., Ma, W.-H., Kalaiselvan, S., Lai, K., Bull, D., Blaauw, D.: RazorII: in situ error detection and correction for PVT and SER tolerance. IEEE J. Solid-State Circuits 44(1), 32–48 (2009)CrossRef
26.
Zurück zum Zitat Omaña, M., Rossi, D., Bosio, N., Metra, C.: Low cost NBTI degradation detection and masking approaches. IEEE Trans. Comput. 62(3), 496–509 (2013)MathSciNetCrossRef Omaña, M., Rossi, D., Bosio, N., Metra, C.: Low cost NBTI degradation detection and masking approaches. IEEE Trans. Comput. 62(3), 496–509 (2013)MathSciNetCrossRef
27.
Zurück zum Zitat Lin, Y., Zwolinski, M.: SETTOFF: a fault tolerant flip-flop for building cost-efficient reliable systems. In: IEEE International On-Line Testing Symposium, pp. 7–12 (2012) Lin, Y., Zwolinski, M.: SETTOFF: a fault tolerant flip-flop for building cost-efficient reliable systems. In: IEEE International On-Line Testing Symposium, pp. 7–12 (2012)
28.
29.
Zurück zum Zitat Semião, J., Freijedo, J., Rodríguez Andina, J.J., Vargas, F., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits. In: IOLTS 2008 - 14th IEEE International On-Line Testing Symposium, Rhodes, 7–9 July 2008 Semião, J., Freijedo, J., Rodríguez Andina, J.J., Vargas, F., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Exploiting parametric power supply and/or temperature variations to improve fault tolerance in digital circuits. In: IOLTS 2008 - 14th IEEE International On-Line Testing Symposium, Rhodes, 7–9 July 2008
30.
Zurück zum Zitat Semião, J., Romão, A., Saraiva, D., Leong, C., Santos, M., Teixeira, I., Teixeira, P.: Performance sensor for tolerance and predictive detection of delay-faults. In: Accepted for Publication in the DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) Symposium 2014, Amsterdam, The Netherlands, 1–3 October 2014. http://dx.doi.org/10.1109/DFT.2014.6962092 Semião, J., Romão, A., Saraiva, D., Leong, C., Santos, M., Teixeira, I., Teixeira, P.: Performance sensor for tolerance and predictive detection of delay-faults. In: Accepted for Publication in the DFT (International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems) Symposium 2014, Amsterdam, The Netherlands, 1–3 October 2014. http://​dx.​doi.​org/​10.​1109/​DFT.​2014.​6962092
31.
Zurück zum Zitat Semiao, J., Freijedo, J., Rodriguez-Andina, J.J., Vargas, F., Santos, M., Teixeira, I., Teixeira, J.P.: Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies. In: Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), Held in Sesimbra, Portugal, 24–26 June 2009, pp. 223–228, ISBN 978-1-4244-4822-7. http://dx.doi.org/10.1109/IOLTS.2009.5196020 Semiao, J., Freijedo, J., Rodriguez-Andina, J.J., Vargas, F., Santos, M., Teixeira, I., Teixeira, J.P.: Delay-fault tolerance to power supply voltage disturbances analysis in nanometer technologies. In: Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), Held in Sesimbra, Portugal, 24–26 June 2009, pp. 223–228, ISBN 978-1-4244-4822-7. http://​dx.​doi.​org/​10.​1109/​IOLTS.​2009.​5196020
32.
Zurück zum Zitat Cavalaria, H., Cabral, R., Semião, J., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Power-delay analysis for subthreshold voltage operation. In: Mortal, A., Aníbal, J., Monteiro, J., Sequeira, C., Semião, J., Moreira da Silva, M., Oliveira, M. (eds.) INCREaSE 2017, pp. 369–386. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-70272-8_30CrossRef Cavalaria, H., Cabral, R., Semião, J., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Power-delay analysis for subthreshold voltage operation. In: Mortal, A., Aníbal, J., Monteiro, J., Sequeira, C., Semião, J., Moreira da Silva, M., Oliveira, M. (eds.) INCREaSE 2017, pp. 369–386. Springer, Cham (2018). https://​doi.​org/​10.​1007/​978-3-319-70272-8_​30CrossRef
33.
Zurück zum Zitat Cabral, R., Cavalaria, H., Semião, J., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Performance sensor for subthreshold voltage operation. In: Mortal, A., Aníbal, J., Monteiro, J., Sequeira, C., Semião, J., Moreira da Silva, M., Oliveira, M. (eds.) INCREaSE 2017, pp. 387–402. Springer, Cham (2018). https://doi.org/10.1007/978-3-319-70272-8_31CrossRef Cabral, R., Cavalaria, H., Semião, J., Santos, M.B., Teixeira, I.C., Teixeira, J.P.: Performance sensor for subthreshold voltage operation. In: Mortal, A., Aníbal, J., Monteiro, J., Sequeira, C., Semião, J., Moreira da Silva, M., Oliveira, M. (eds.) INCREaSE 2017, pp. 387–402. Springer, Cham (2018). https://​doi.​org/​10.​1007/​978-3-319-70272-8_​31CrossRef
34.
Zurück zum Zitat Semião, J., Romão, A., Leong, C., Santos, M., Teixeira, I., Teixeira, P.: Aging-aware dynamic voltage or frequency scaling. In: Proceedings of the XXIX Conference on Design of Circuits and Integrated Systems (DCIS 2014), Madrid, Spain, 26–28 November 2014. http://dx.doi.org/10.1109/DCIS.2014.7035599 Semião, J., Romão, A., Leong, C., Santos, M., Teixeira, I., Teixeira, P.: Aging-aware dynamic voltage or frequency scaling. In: Proceedings of the XXIX Conference on Design of Circuits and Integrated Systems (DCIS 2014), Madrid, Spain, 26–28 November 2014. http://​dx.​doi.​org/​10.​1109/​DCIS.​2014.​7035599
Metadaten
Titel
Performance Sensor for Reliable Operation
verfasst von
Jorge Semião
Ruben Cabral
Marcelino B. Santos
Isabel C. Teixeira
J. Paulo Teixeira
Copyright-Jahr
2018
DOI
https://doi.org/10.1007/978-3-319-92052-8_28

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