Performance Study of an Integrated Packet Switch with Two Priority Classes

This paper presents an analysis of an N×N, internally non-blocking packet switch with two different priority classes. The analysis extends methods developed in recent publications for systems with a single priority class. A possible application of this work is in the analysis of integrated packet switches that support both voice and data traffic with different priorities. The switch is operated in a slotted fashion, and the probabilities of packet arrival in a time slot are distinct for the two priority classes. Low priority packets can be queued. High priority packets are cleared from the system in case of unsuccessful transmission through the switch. The results developed in the paper provide performance measures such as blocking probabilities and average delays. Expressions for system stability and total throughput are also studied in terms of both high and low priority traffic loads. Numerical examples illustrate the results.