Physical Design and Mask Synthesis for Directed Self-Assembly Lithography

In DSAL, contacts (or vias) are patterned in two steps. A GP that surrounds a group of nearby contacts forms on a wafer through optical lithography; member contacts then form through DSA process that arises within a GP. Final contact shape can be predicted by two sequential simulations: lithography simulation to predict GP shape and DSA simulation to predict contact. In reality, the two simulations should be repeated to account for lithography as well as DSA variations.

In DSAL, each group of contacts (or vias) is associated with a GP. The number of member contacts and their relative position determine the shape of GP. Some GPs, for instance of those with asymmetric shape, have high DSA defect probability as addressed in Sect. 2.​2, and have to be avoided. In standard cell based design, if such GPs are discovered within a cell, library designers are responsible to fix. If they are discovered at cell boundary when two cells are abutted after placement, a simplest approach to fix is to insert whitespace. It turns out that too many cell pairs require whitespace. In this chapter, two placement techniques are presented. In post-placement optimization (Shim et al., in Proceedings of the International Conference on Computer Aided Design, pp. 404–409, 2015, [1]), some cells are flipped and some two cells swap their position so that the number of cell pairs that require whitespace is minimized. In automatic placement, defect probability is taken care of while placement is performed. It is demonstrated that the two techniques yield layout of higher density (or less whitespace) by about 11–12% compared to layout of simple-minded approach.

Sub 7-nm technology node requires small contacts whose size and pitch are beyond optical resolution limit. Such fine features can be created by directed self-assembly lithography with multiple patterning (MP-DSAL). In MP-DSAL, layout decomposition is a key problem, in which contacts that are physically close are clustered to form a GP which is then assigned to one of masks. Many practical contact layouts are not MP-DSAL compliant in a sense that layout decomposition is not perfectly performed leaving a few MP coloring conflicts and GPs of non-zero defect probability. This chapter introduces placement optimization to make a layout MP-DSAL compliant. The optimization problem is formulated as ILP, and a practical heuristic is also presented.

In DSAL, vias that are physically close are clustered and patterned together through a guide pattern (GP) [1, 2]. A large and complex GP is not allowed to form because it is likely to cause a pattern failure on a wafer. This chapter addresses redundant via insertion problem for DSAL. The goal is to maximally insert redundant vias while vias (both original and redundant) are clustered to form only desirable GPs. The problem can be formulated as finding maximum independent set (MIS) of a conflict graph. Experiments demonstrate that 13% more redundant vias are inserted compared to simple-minded approach, in which a basic insertion with no consideration of DSAL is followed by removal of redundant vias that cause undesirable GPs. DSA defect probability of via cluster is addressed in order to quantitatively define which GPs are allowed during the redundant via insertion process.

In MP-DSAL, vias that are physically close are clustered to form a GP and patterned together through DSAL process; in addition, GPs that are too close are created on a wafer using different masks through MP. It should be very careful to insert redundant vias in MP-DSAL since some redundant vias may cause large and complex via clusters, whose GPs is likely to cause DSA defect; some other redundant vias may cause MP coloring conflict. This chapter addresses redundant via insertion for MP-DSAL, which aims to insert maximum number of redundant vias while all GPs are manufacturable and no MP coloring conflict occur. The problem can be formulated as ILP, which is used as a reference for comparison to a graph-based heuristic algorithm.

In DSAL, a mask contains the image of guide patterns (GPs) not the image of final contacts or vias. Thus, a wafer receives GP patterns after optical lithography is applied to the mask. It then goes through a DSA process, and contacts are finally patterned. Mask design for DSAL, which is, in fact, the opposite of the above-mentioned process, consists of two key steps, inverse DSA and inverse lithography. In inverse DSA, GPs are progressively refined until they are estimated to produce contacts that are close to target ones as much as possible. For this purpose, GP is defined as a function of a few geometry parameters, and the sensitivity of contact to each parameter is repeatedly calculated to guide how much GP should be refined. In inverse lithography, mask is progressively refined until it is believed to produce target GPs. Mask is defined by a grid of pixel values (rather than by a set of edges) and their gradient guides the direction that the mask should be refined. There are typically too many pixels for gradient calculation; the method to approximate calculation is described in this chapter. Inverse DSA and inverse lithography are extended to handle process variations. The basic inverse lithography is modified so that the resulting mask becomes less sensitive to lithography variations; basic inverse DSA is modified so that it provides the way this sensitivity can be checked.

Guide patterns (GPs) are very critical in contacts (and vias) patterning in directed self-assembly lithography (DSAL). Simulations may be used to verify whether each GP will lead to correct patterning of its member contacts, but runtime is excessive. Instead, the shape of GP can be characterized using some geometric parameters. Then, a function for the verification can be constructed to predict whether the required contacts can be obtained by a GP (Shim et al., Proceedings for SPIE Advanced Lithography, pp. 1–8, 2015, [1], Azat, Proceedings for SPIE Advanced Lithography, pp. 1–10, 2013, [2]). Specifically, each GP in a test set is represented as a vector in parameter space; DSA simulation is applied to each GP assessing its acceptability, and corresponding vector is marked “good” or “bad” accordingly; the parameter space is deformed in a way that a radial distribution is converted into one in which the good and bad vectors can be successfully separated by a certain hyperplane, which finally becomes the verification function. It is also shown that principal component analysis (PCA) can be applied for reducing the dimensionality of the parameter space, and the characterization of GPs can be generalized to allow different types of GP to be verified in a unified fashion. Such methods are demonstrated in 10 nm technology.

Line-end cut process is used to create very fine metal wires in sub-14 nm technology. Cut patterns split regularly spaced line patterns into a number of wire segments, some of which become actual routing wires while the remainders are regarded as dummy. In sub-10 nm technology, cuts are smaller than optical resolution limit and a directed self-assembly lithography with multiple patterning (MP-DSAL) is a good candidate for their patterning. Cut optimization for MP-DSAL is addressed in this chapter. The optimization goal is to determine cut locations in such a way that cuts are grouped into manufacturable GPs, which are then assigned to one of the masks without MP coloring conflicts; minimizing wire extensions is also pursued in the process. The optimization problem is formulated as ILP and a fast heuristic algorithm is also presented.

In DSAL, contacts (or vias) are indirectly formed through guide patterns (GPs). Thus, the integrity of GP is very important to obtain desirable contacts on a wafer. Since GP is created by traditional lithography, it may have some errors when its shape is large and complex (Shim and Shin, Proceedings of the International Conference on Very Large Scale Integration (VLSI-SoC) (2015), Shim, Chung and Shin, Proceedings of the International Conference on Computer Aided Design (2015)) [1, 2], which affect final contact patterns. Such limitation of GP shape calls for careful considerations in physical design. It has been also argued that conventional mask synthesis and verification for traditional lithography are obsolete in DSAL. In this context, this book has addressed problems on physical design and mask synthesis as follows.