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2018 | OriginalPaper | Buchkapitel

6. Redundant Via Insertion for MP-DSAL

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Abstract

In MP-DSAL, vias that are physically close are clustered to form a GP and patterned together through DSAL process; in addition, GPs that are too close are created on a wafer using different masks through MP. It should be very careful to insert redundant vias in MP-DSAL since some redundant vias may cause large and complex via clusters, whose GPs is likely to cause DSA defect; some other redundant vias may cause MP coloring conflict. This chapter addresses redundant via insertion for MP-DSAL, which aims to insert maximum number of redundant vias while all GPs are manufacturable and no MP coloring conflict occur. The problem can be formulated as ILP, which is used as a reference for comparison to a graph-based heuristic algorithm.

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Fußnoten
1
Remind that via partitions are the input of each method as an input as presented in Sect. 6.2.1.
 
Literatur
1.
Zurück zum Zitat H. Yi, X. Bao, R. Tiberio, P. Wong, Design strategy of small topographical guiding templates for sub-15 nm integrated circuits contact hole patterns using block copolymer directed self-assembly, in Proceedings of the SPIE Advanced Lithography, pp. 1–9 (2013) H. Yi, X. Bao, R. Tiberio, P. Wong, Design strategy of small topographical guiding templates for sub-15 nm integrated circuits contact hole patterns using block copolymer directed self-assembly, in Proceedings of the SPIE Advanced Lithography, pp. 1–9 (2013)
2.
Zurück zum Zitat L. Azat, G. Grant, P. Moshe, S. Gerard, W. Wong, J. Xu, Y. Zou, Computational simulations and parametric studies for directed self-assembly process development and solution of the inverse directed self-assembly problem. Jpn. J. Appl. Phys. 53(6S), 1–8 (2014) L. Azat, G. Grant, P. Moshe, S. Gerard, W. Wong, J. Xu, Y. Zou, Computational simulations and parametric studies for directed self-assembly process development and solution of the inverse directed self-assembly problem. Jpn. J. Appl. Phys. 53(6S), 1–8 (2014)
3.
Zurück zum Zitat S. Shim, W. Chung, Y. Shin, Defect probability of directed self-assembly lithography: fast identification and post-placement optimization, in Proceedings of the International Conference on Computer Aided Design, pp. 404–409 (2015) S. Shim, W. Chung, Y. Shin, Defect probability of directed self-assembly lithography: fast identification and post-placement optimization, in Proceedings of the International Conference on Computer Aided Design, pp. 404–409 (2015)
4.
Zurück zum Zitat W. Chung, S. Shim, Y. Shin, Redundant via insertion in directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 55–60 (2016) W. Chung, S. Shim, Y. Shin, Redundant via insertion in directed self-assembly lithography, in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp. 55–60 (2016)
5.
Zurück zum Zitat Y. Badr, A. Torres, Y. Ma, J. Mitra, P. Gupta, Incorporating DSA in multipatterning semiconductor manufacturing technologies, in Proceedings of the SPIE Advanced Lithography, pp. 1–8 (2015) Y. Badr, A. Torres, Y. Ma, J. Mitra, P. Gupta, Incorporating DSA in multipatterning semiconductor manufacturing technologies, in Proceedings of the SPIE Advanced Lithography, pp. 1–8 (2015)
6.
Zurück zum Zitat Y. Badr, A. Torres, P. Gupta, Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7 nm contacts/vias, in Proceedings of the Design Automation Conference, pp. 70:1–70:6 (2015) Y. Badr, A. Torres, P. Gupta, Mask assignment and synthesis of DSA-MP hybrid lithography for sub-7 nm contacts/vias, in Proceedings of the Design Automation Conference, pp. 70:1–70:6 (2015)
7.
Zurück zum Zitat S. Shim, W. Chung, Y. Shin, Redundant via insertion for multiple-patterning directed-self-assembly lithography, in Proceedings of the Design Automation Conference, pp. 41:1–41:6 (2016) S. Shim, W. Chung, Y. Shin, Redundant via insertion for multiple-patterning directed-self-assembly lithography, in Proceedings of the Design Automation Conference, pp. 41:1–41:6 (2016)
8.
Zurück zum Zitat J. Gyvez, Yield modeling and BEOL fundamentals, in Proceedings of the International Workshop on System-Level Interconnect Prediction, pp. 135–163 (2001) J. Gyvez, Yield modeling and BEOL fundamentals, in Proceedings of the International Workshop on System-Level Interconnect Prediction, pp. 135–163 (2001)
9.
Zurück zum Zitat K. Lee, T. Wang, Post-routing redundant via insertion for yield/reliability improvement, in Proceedings of the Asia South Pacific Design Automation Conference, pp. 303–308 (2006) K. Lee, T. Wang, Post-routing redundant via insertion for yield/reliability improvement, in Proceedings of the Asia South Pacific Design Automation Conference, pp. 303–308 (2006)
10.
Zurück zum Zitat C. Pan, Y. Lee, Redundant via insertion under timing constraints, in Proceedings of the International Symposium on Quality Electronic Design, pp. 1–7 (2011) C. Pan, Y. Lee, Redundant via insertion under timing constraints, in Proceedings of the International Symposium on Quality Electronic Design, pp. 1–7 (2011)
11.
Zurück zum Zitat J. Yan, Z. Chen, B. Chiang, Y. Lee, Timing-constrained yield-driven redundant via insertion, in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, pp. 1688–1691 (2008) J. Yan, Z. Chen, B. Chiang, Y. Lee, Timing-constrained yield-driven redundant via insertion, in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, pp. 1688–1691 (2008)
12.
Zurück zum Zitat S. Fang, Y. Hong, Y. Lu, Simultaneous guiding template optimization and redundant via insertion for directed self-assembly, in Proceedings of the International Conference on Computer Aided Design, pp. 410–417 (2015) S. Fang, Y. Hong, Y. Lu, Simultaneous guiding template optimization and redundant via insertion for directed self-assembly, in Proceedings of the International Conference on Computer Aided Design, pp. 410–417 (2015)
13.
Zurück zum Zitat S. Sakai, M. Togasaki, K. Tamazaki, A note on greedy algorithm for the maximum weighted independent set problem. Discret. Appl. Math. 126(2), 313–322 (2003)CrossRef S. Sakai, M. Togasaki, K. Tamazaki, A note on greedy algorithm for the maximum weighted independent set problem. Discret. Appl. Math. 126(2), 313–322 (2003)CrossRef
14.
Zurück zum Zitat Calibre Multi-Patterning Manual, Mentor Graphics, Jan. 2013 Calibre Multi-Patterning Manual, Mentor Graphics, Jan. 2013
Metadaten
Titel
Redundant Via Insertion for MP-DSAL
verfasst von
Seongbo Shim
Youngsoo Shin
Copyright-Jahr
2018
DOI
https://doi.org/10.1007/978-3-319-76294-4_6

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