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As Moore’s law continues to unfold, two important trends have recently emerged. First, the growth of chip capacity is translated into a corresponding increase of number of cores. Second, the parallelization of the computation and 3D integration technologies lead to distributed memory architectures. This book describes recent research that addresses urgent challenges in many-core architectures and application mapping. It addresses the architectural design of many core chips, memory and data management, power management, design and programming methodologies. It also describes how new techniques have been applied in various industrial case studies.



HW/SW/ Building Blocks: Architecture, Methods, and Techniques


Chapter 1. Memory Architecture and Management in an NoC Platform

The memory organization and the management of the memory space is a critical part of every NoC based platform design. We propose a Data Management Engine (DME), that is a block of programmable hardware and part of every processing element. It off-loads the processing element (CPU, DSP, etc.) by managing the memory space, memory access and the communication over the on-chip network. The DME’s main functions are virtual address translation, private and shared memory management, cache coherence protocol, support for memory consistency models, synchronization and protection mechanisms for shared memory communication. The DME is fully programmable and configurable thus allowing for customized support for high level data management functions such as dynamic memory allocation and abstract data types. This chapter describes the main concepts, design and functionality of the DME and presents case studies illustrating its usage and performance.

Axel Jantsch, Xiaowen Chen, Abdul Naeem, Yuang Zhang, Sando Penolazzi, Zhonghai Lu

Chapter 2. Application-Specific Multi-Threaded Dynamic Memory Management

This chapter presents the methodology and the corresponding software framework developed to systematically explore the design space of Multi-Threaded Dynamic Memory Management (MTh-DMM). We developed two exploration approaches: (a) a two-phase constraint-orthogonal and (b) a single-phase aggressive exploration methodologies. Pareto optimal configurations are generated considering various design targets. Experimental results evaluate the solution quality delivered by the proposed exploration approaches and by state-of-the art general purpose dynamic memory management solutions, based on a real-life multi-threaded network application.

Sotirios Xydis, Alexandros Bartzas, Iraklis Anagnostopoulos, Dimitrios Soudris

Chapter 3. Power Management Architecture in McNoC

In this chapter we present the power management architecture of the McNoC platform. The power management architecture of McNoC offers distributed Dynamic Voltage Frequency Scaling (DVFS) and power down services to the platform at a fine level of granularity, allowing independent setting of frequency and supply voltage to all switch and resource nodes in the platform. The design style enables hierarchical physical design and solves the clock-domain-crossing problem with a solution based on rationally-related frequencies, which avoids the overhead associated with handshake. The architecture allows arbitrary power management regions to be defined and region-wide power management commands affecting all nodes in a region can be issued by the software layer that we call as Power Management Intelligence (PMINT).

Jean-Michel Chabloz, Ahmed Hemani

Chapter 4. ASIP Exploration and Design

ASIP exploration uses the mappability method for the selection of processor core and algorithm combinations for multi-core designs. The mappability estimation is based on the analysis of the correlations of algorithm and core characteristics. This information is used for narrowing the exploration space of the subsequent ASIP design that exploits commercial ASIP design environment, Synopsys Processor Designer. According to simulation results the proposed ASIPs are able to achieve up to 96% of maximum performance with a clear reduction in complexity.

Jari Kreku, Kari Tiensyrjä, Andreas Wieferink, Bart Vanthournout

System-level Exploration


Chapter 5. System Exploration

Future embedded system products, e.g. smart handheld mobile terminals, will accommodate a large number of applications that will partly run sequentially and independently, partly concurrently and interacting on massively parallel computing platforms. Already for systems of moderate complexity, the design space will be huge and its exploration requires that the system architect is able to quickly evaluate the performances of candidate architectures and application mappings. The mainstream evaluation technique today is the system-level performance simulation of the applications and platforms using abstracted workload and processing capacity models, respectively. These virtual system models allow fast simulation of large systems at an early phase of development with reasonable modelling effort and time. The accuracy of the performance results is dependent on how closely the models used reflect the actual system. This chapter gives a description of the ABSOLUT modelling and simulation approach. Firstly, it gives an outline view of the approach and its evolution. Secondly, it describes how to create different models. Thirdly, it describes the means for simulation.

Jari Kreku, Kari Tiensyrjä

Chapter 6. MPA: Parallelization Made Easy

This chapter of the book covers the work performed on IMEC’s parallelization tool called MPA. The work done on this tool in the context of the MOSART Project involved several extensions to an already existing baseline version of the MPA tool. In this section we will give an introduction to the entire MPA parallelization tool, and briefly compare our approach to some of the existing alternatives for doing application parallelization. All developed extension in the context of this project will also be explained in more detail. Finally we will conclude this book chapter with a simple example to illustrate the most interesting features of IMEC’s parallelization tool.

Geert Vanmeerbeeck, Thomas J. Ashby

Industrial Applications


Chapter 7. MPSoC Architecture Performance Analysis for Agile SDR Radio Applications

With the endless transformation of telecommunications in the last decades by the market (higher connectivity, deregulation, globalization, more mobility and new services) and related technology innovations, ubiquitous access to all types of media, data, audio or video is becoming a reality.

Sylvain Aguirre, Bernard Candaele

Chapter 8. Application of the MOSART Flow on the WiMAX (802.16e) PHY Layer

Current and emerging telecommunication standards require the fast and efficient design of large hardware/software systems that need to bring together diverse engineering skills. MOSART offers a solution to the problem of fast design of large systems by converting the current design cycle into the transformation of an executable reference specification to software optimized for execution on tailored multiprocessor platforms. ICOM has tested this approach using as test-bed a part of the PHY layer for the 802.16e (WiMAX) standard; a strategic roadmap system for INTRACOM. Use method and experimental results are reported for this exercise.

Frank Ieromnimon, Dimitrios Kritharidis, Nikolaos S. Voros
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