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2001 | Buch

Scanning Probe Lithography

verfasst von: Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate

Verlag: Springer US

Buchreihe : Microsystems

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Über dieses Buch

Scanning Probe Lithography (SPL) describes recent advances in the field of scanning probe lithography, a high resolution patterning technique that uses a sharp tip in close proximity to a sample to pattern nanometer-scale features on the sample. SPL is capable of patterning sub-30nm features with nanometer-scale alignment registration. It is a relatively simple, inexpensive, reliable method for patterning nanometer-scale features on various substrates. It has potential applications for nanometer-scale research, for maskless semiconductor lithography, and for photomask patterning.
The authors of this book have been key players in this exciting new field. Calvin Quate has been involved since the beginning in the early 1980s and leads the research time that is regarded as the foremost group in this field. Hyongsok Tom Soh and Kathryn Wilder Guarini have been the members of this group who, in the last few years, have brought about remarkable series of advances in SPM lithography. Some of these advances have been in the control of the tip which has allowed the scanning speed to be increased from mum/second to mm/second. Both non-contact and in-contact writing have been demonstrated as has controlled writing of sub-100 nm lines over large steps on the substrate surface. The engineering of a custom-designed MOSFET built into each microcantilever for individual current control is another notable achievement. Micromachined arrays of probes each with individual control have been demonstrated. One of the most intriguing new aspects is the use of directly-grown carbon nanotubes as robust, high-resolution emitters.
In this book the authors concisely and authoritatively describe the historical context, the relevant inventions, and the prospects for eventual manufacturing use of this exciting new technology.

Inhaltsverzeichnis

Frontmatter
Chapter 1. Introduction to Scanning Probe Lithography
Abstract
Semiconductor lithography is the patterning process used to define the structures that make up integrated circuits (ICs). The semiconductor industry has historically scaled down the size of printed features on ICs because scaling both improves transistor performance and reduces the area that devices occupy. Today the patterning technology employed in manufacturing is photolithography, a process that uses ultraviolet light to define submicron-sized features in photosensitive polymers. Since photolithography is rapidly approaching fundamental resolution limitations, a new high-resolution patterning technique may be required to continue the industry’s trend toward higher performance electron devices, increased packing densities, and higher density memories.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 2. SPL by Electric-Field- Enhanced Oxidation
Abstract
SPL by electric-field-enhanced oxidation was introduced by Dagata [5] in his pioneering study of patterning hydrogen passivated <111> single crystal silicon with the scanning tunneling microscope (STM). The lithography begins by removing the native oxide and hydrogen passivating the silicon surface in hydroflouric acid (HF). Then the tip of a scanning probe with a voltage bias (typically a few volts) is brought to the vicinity of the surface creating an intense electric field. The magnitude of this electric field can be in excess of 1 V/nm. A schematic diagram of the experimental set up is shown in Fig. 2.1.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 3. Resist Exposure Using Field-Emitted Electrons
Abstract
Early scanning probe lithography (SPL) studies were limited to demonstrations of the technique’s fine resolution. A few groups fabricated devices using SPL [1][2][3], but such work was directed toward creating a single working device suitable for research or exploration. Methods used by these groups suffer from speed constraints and poor repeatability, thus it is unlikely they can be easily extended to large-scale fabrication applications. We sought to develop a method of SPL suited to semiconductor lithography, where accuracy, reliability, and throughput are essential.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 4. SPL Linewidth Control
Abstract
The current-controlled scanning probe lithography (SPL) systems that we developed (described in Chapter 3) can reliably pattern uniform features in organic resists with dimensions below 100 nm. In this chapter, we compare electron exposures made by SPL to those made by electron beam lithography (EBL). This comparison highlights the advantages and limitations of a low-energy electron lithography technique such as SPL.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 5. Critical Dimension Patterning Using SPL
Abstract
Transistor gate patterning is the primary application of a high-resolution lithographic system in the semiconductor industry. The gate itself is typically a long, narrow line of polysilicon whose width (known as the transistor gate “length”) determines the device switching speed. The uniformity of the gate is critical for device electrical performance and yield. Gate patterning is performed after significant device processing. Therefore the feature must be accurately aligned to the previously patterned regions. It must also be written over the sample topography created by the prior fabrication steps.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 6. High Speed Resist Exposure With a Single Tip
Abstract
We have shown that current-controlled scanning probe lithography (SPL) can reliably pattern nanometer-scale features in resist. However, the serial nature of SPL makes it much slower than mask-based techniques such as photolithography, x-ray lithography, or extreme ultraviolet lithography. An advantage of a direct write approach is that it does not require expensive and time-consuming mask fabrication. SPL may also have superior alignment capabilities. Nevertheless, in order for SPL to become a viable technology for high-resolution semiconductor lithography, the throughput must be dramatically increased.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 7. On-Chip Lithography Control
Abstract
Our preferred method of scanning probe lithography (SPL) uses electrons field emitted from a micromachined probe tip in air to expose organic polymer resists. The pattern dimension is set by the electron exposure dose delivered to the resist. Control of the exposure dose has been achieved previously through external feedback circuitry. Typically the emission current is measured and compared with the desired (or setpoint) current. A signal is sent to adjust either the tip-sample voltage [1–3] or the tip-sample distance [4–6] in order to ensure that the measured current does not deviate significantly from the setpoint. In place of this feedback circuitry, we integrated a transistor current source onto the cantilever chip to control the electron exposure dose delivered to the resist. In this chapter we describe the design, fabrication, and operation of this integrated current source.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 8. Scanning Probe Tips for SPL
Abstract
This chapter presents the required features of probe tips for scanning probe lithography (SPL) and some novel methods for tip fabrication. For both field-induced oxidation and electron exposure SPL, probe tips must be electrically conductive and sharp to enable field concentration at the tip apex. For field emission of electrons from the tips, the workfunction of the tip material is significant. In the case of feedback control of the emitted current, the tips should be tall to ensure a small cantilever-to-sample capacitance. In this chapter we give details on different tip varieties: (1) “standard” silicon or metal-coated tips, (2) post-processed silicon tips, and (3) carbon nanotubes as scanning probe tips.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Chapter 9. Scanning Probe Arrays for Lithography
Abstract
In Chapter 6 we demonstrated dramatic improvements in the writing speed of a single tip, yet patterning throughput is still too low to make SPL a viable large-scale patterning technology. For example, a writing speed of 10 mm/s and a pixel size of 100 nm correspond to a pixel rate of 100 kHz (kilopixels per second). An exposure field measuring 1 cm × 1 cm contains 1010 pixels. If we raster scanned the tip over every pixel in the exposure field, it would take 105 seconds or about one day to cover the region. For comparison, today’s deep ultraviolet (DUV) steppers pattern about 40 200-mm-diameter wafers per hour. Each wafer contains more than 200 1 cm × 1 cm exposure fields.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Epilog
Abstract
Patterning nanoscale features with a size less that 100 nm falls into the domain occupied by electron beam lithography (EBL). This is a mature technology with software in place, but it is restricted in several areas. It is not easy to pattern feature sizes below 30 nm. The proximity effect makes it difficult to place fine lines close to each other. With the large depth of focus it is difficult to register patterns with sub-100 nm features as required for overlay with multiple layers. The primary restriction is that of throughput. The EBL system is not often used for patterning multiple copies. It takes too long to write patterns over modest areas. For example, it may take four hours to fill one square centimeter with 50 nm dots spaced by 20 microns. Furthermore, the SEM is not readily configured for arrays which the barrier for reaching high throughput with this technology.
Hyongsok T. Soh, Kathryn Wilder Guarini, Calvin F. Quate
Backmatter
Metadaten
Titel
Scanning Probe Lithography
verfasst von
Hyongsok T. Soh
Kathryn Wilder Guarini
Calvin F. Quate
Copyright-Jahr
2001
Verlag
Springer US
Electronic ISBN
978-1-4757-3331-0
Print ISBN
978-1-4419-4894-6
DOI
https://doi.org/10.1007/978-1-4757-3331-0