Skip to main content

1994 | Buch

Scrambling Techniques for Digital Transmission

verfasst von: Byeong Gi Lee, BS, ME, PhD, Seok Chang Kim, BS, ME, PhD

Verlag: Springer London

Buchreihe : Telecommunication Networks and Computer Systems

insite
SUCHEN

Über dieses Buch

Scramblers and shift register generators (SRG) have been used for decades in the shaping of digital transmission signals and in generating pseudo-random binary sequences for transmission applications. In recent years more attention has been paid to this area than ever before due to the change of today's telecommunication environment. This publication presents the theory and applications of three scrambling techniques - Frame Synchronous Scrambling (FSS), Distributed Sample Scrambling (DSS) and Self Synchronous Scrambling (SSS) with an emphasis on their application in digital transmission. Based on the authors' research over the past ten years, this is the first book of its kind.

Inhaltsverzeichnis

Frontmatter

Preliminaries

Frontmatter
Chapter 1. Digital Transmission and Scrambling
Abstract
Digital transmission is a technique that transmits information signals in a stream of digital pulses. The original signals may be in analog or digital form, and the transmission medium may be copper wire or optical fiber based. In either case, as long as the signals are conveyed in digital pulse stream over the transmission medium, it is called digital transmission.
Byeong Gi Lee, Seok Chang Kim
Chapter 2. Fundamentals of Scrambling Techniques
Abstract
Scrambling is a binary bit-level processing applied to the transmission rate signal in order to make the resulting binary sequence appear more random. The scrambler performing this scrambling function can be implemented simply using a few shift registers and exclusive-OR gates; and the descramblers reconstructing the original bitstream out of the scrambled data stream has the same structure but with the reversed data flow. For a proper reconstruction of the original bitstream the shift registers in the descrambler should get synchronized to their counterparts in the scrambler. Depending on the synchronization method used, scrambling techniques are classified into three categories, namely the frame-synchronous scrambling(FSS), the distributed sample scrambling(DSS), and the self-synchronous scrambling(SSS).1 In the FSS, the states of the scrambler and the descrambler shift registers get synchronized by being simultaneously reset to the prespecified states at the start of each frame; in the DSS, samples taken from the scrambler shift registers are transmitted to the descrambler in a distributed manner for use in synchronizing the descrambler shift registers; and in the SSS, the states of the scrambler and descrambler shift registers are automatically synchronized without any additional synchronization processes.
Byeong Gi Lee, Seok Chang Kim

Frame Synchronous Scrambling

Frontmatter
Chapter 3. Introduction to Frame Synchronous Scrambling
Abstract
Frame synchronous scrambling (FSS) is a scrambling technique which employs SRGs generating PRBSs for use in scrambling as well as in descrambling of the data bitstream. For the synchronization of the SRGs it resets the SRG states to some prespecified states at every frame start. Due to this resetting operation, FSS is suitable for scrambling of framed signals, and the scrambling effect is better for larger-sized frames.
Byeong Gi Lee, Seok Chang Kim
Chapter 4. Sequence Spaces
Abstract
In this chapter, we introduce the concept of sequence space as a means to rigorously describe the behaviors of sequences and SRGs. A sequence space is a vector space whose elements are sequences satisfying the relation specified by a characteristic polynomial. For a sequence space, there are two bases, namely, the elementary basis and the primary basis, which form the framework of the space. In addition, the polynomial expression of sequences renders a useful tool for mathematical manipulations within the sequence spaces. Based on these new concepts, we investigate various aspects of sequence spaces, such as sequence subspaces and minimal sequence spaces.
Byeong Gi Lee, Seok Chang Kim
Chapter 5. Shift Register Generators
Abstract
Shift register generator (SRG) is an autonomous system consisting of shift registers and exclusive-OR gates. In this chapter, we investigate the behaviors of SRGs in view of the sequence space theory developed in the previous chapter. For a given SRG, we first consider how to determine the sequence space generated by SRG sequences with a fixed initial state vector (SRG space), and then consider how to find the largest-dimensional sequence space that can be obtained by varying the initial state vectors (SRG maximal space). Conversely, for a given sequence space we consider how to find the minimum-sized SRGs that can generate the sequence space (basic SRG). Finally, we examine the two typical SRGs, namely the simple SRG and the modular SRG, in view of the concept of basic SRGs.
Byeong Gi Lee, Seok Chang Kim
Chapter 6. Serial Frame Synchronous Scrambling
Abstract
In the frame synchronous scrambling (FSS), the input data bitstream is scrambled by adding a pseudo-random binary sequence (PRBS) to this, and the scrambled data bitstream is descrambled by adding the same PRBS to this. In this chapter, we examine the behaviors of PRBSs in view of the sequence space theory developed in Chapter 4, and consider how to realize SRGs that generate PRBSs based on the SRG theory developed in Chapter 5. We will first define PRBS systematically using the mathematical definitions of weight, run and autocorrelation of sequences. Then, we will consider a special class of sequence spaces, namely the primitive sequence spaces, whose characteristic polynomials are primitive, showing that the sequences in the primitive sequence spaces are PRBSs. Finally, we will consider how to realize SRGs that generate PRBSs in the primitive sequence spaces.
Byeong Gi Lee, Seok Chang Kim
Chapter 7. Parallel Frame Synchronous Scrambling
Abstract
In the parallel frame synchronous scrambling (PFSS), the parallel input data bitstreams are scrambled before multiplexing, and the scrambled data bitstream is descrambled after demultiplexing. In this chapter, we discuss the behaviors of parallel scrambling sequences for use in the parallel scrambling in view of the sequence space theory developed in Chapter 4, and consider how to realize SRGs generating parallel scrambling sequences using the SRG theory developed in Chapter 5. We will first show that the parallel scrambling sequences are the decimated sequences of the serial scrambling sequence. Then, we will discuss how to decompose the serial sequence into a linear sum of the so-called irreducible sequence and power sequence, and consider how to determine the decimated sequences of the irreducible and power sequences. We will also examine how to obtain the decimated sequences of the original serial sequences decomposed into the irreducible and power sequences. Finally, we will discuss how to realize parallel SRGs to generate parallel sequences, and consider how to achieve their minimal realizations.
Byeong Gi Lee, Seok Chang Kim
Chapter 8. Multibit-Parallel Frame Synchronous Scrambling
Abstract
Multibit-parallel frame synchronous scrambling (MPFSS) is a generalization of the parallel frame synchronous scrambling (PFSS) in which multiplexing is done multibit based. In this sense the PFSS we have considered so far is a special case of the MPFSS since in the PFSS multiplexing is done single bit based. Multibit-interleaved multiplexing is a scheme widely used these days in lightwave-based digital transmissions such as SDH/SONET (see Chapter 9), and therefore the parallel scrambling in this environment -- that is, the MPFSS -- becomes very important. As in the case of the PFSS, the parallel input data bitstreams are scrambled before multiplexing, and the scrambled data bitstream is descrambled after demultiplexing in the MPFSS. However, since the multiplexer and demultiplexer employed in the MPFSS operate multibit based, the parallel scrambling sequences for use in the MPFSS is quite different from those employed in the PFSS.
Byeong Gi Lee, Seok Chang Kim
Chapter 9. Applications to Scrambling in SDH/SONET Transmission
Abstract
In this chapter, we consider how to apply the serial, parallel and multibitparallel FSS techniques developed in the previous chapters to the SDH and SONET systems, which are the most typical lightwave transmission systems employing the FSS. We first describe the FSS operations used in the SDH and SONET systems along with the frame formats of their transmission signals STM-N and STS-N. Then, we consider how to apply the parallel FSS techniques to the scrambling of the STM-1 and the STS-1 signals such that the scrambling rates can drop to one-eighth of the transmission rates. Finally, we examine how to apply the byteparallel FSS techniques to the scrambling of the various STM-N and STS-N signals to reduce their rates to the STM-1 and the STS-1 rates respectively.
Byeong Gi Lee, Seok Chang Kim

Distributed Sample Scrambling

Frontmatter
Chapter 10. Introduction to Distributed Sample Scrambling
Abstract
Distributed sample scrambling (DSS) is a scrambling technique which employs SRGs for generating scrambling sequences and utilizes distributed samples for synchronizing the SRGs. Differently from the FSS, the DSS keeps scrambling without periodically resetting the SRG states, and therefore the DSS exhibits an excellent scrambling effect for small frame-sized signals.
Byeong Gi Lee, Seok Chang Kim
Chapter 11. Prediction of Scrambling Sequences
Abstract
The DSS is distinctively different from the FSS in that it takes samples out of the scrambler SRG sequences and conveys them to the descrambier for use in determining the state of the descrambler SRG. In this regard, it is important to clearly understand the properties of the scrambling sequences and the relations between the scrambling sequences and their samples.
Byeong Gi Lee, Seok Chang Kim
Chapter 12. Serial Distributed Sample Scrambling
Abstract
In the distributed sample scrambling (DSS), which is identical to the FSS in the scrambling and descrambling operations, the descrambler SRG is synchronized to the scrambler SRG using the transmitted samples of the scrambling sequence. In this chapter, we consider the synchronization process of the serial DSS and examine how to realize the scramblers and the descramblers. For this, we first mathematically model the synchronization process along with the scrambler and descrambler SRGs. Then, for the scramblers we consider how to determine the scrambler SRGs and how to sample the scrambling sequence; and for the descramblers we consider how to determine the descrambler SRGs and how to use the samples for the synchronization, along with their efficient realization methods. Finally, we consider how to design the DSS without employing complex timing circuitry.
Byeong Gi Lee, Seok Chang Kim
Chapter 13. Parallel Distributed Sample Scrambling
Abstract
In the parallel distributed sample scrambling (PDSS), the parallel input data bitstreams are scrambled before multiplexing, and the scrambled data bitstream is descrambled after demultiplexing. In this chapter, we discuss issues involved with the parallel realizations of DSSs. We first consider how to realize the PSRGs for PDSS along with the minimal realizations of PSRGs. Then, we examine how to achieve the parallel sampling along with the concurrent parallel sampling. Finally, we consider the parallel correction, with single, double and multiple corrections occurring in the form of immediate corrections.
Byeong Gi Lee, Seok Chang Kim
Chapter 14. Multibit-Parallel Distributed Sample Scrambling
Abstract
The multibit-parallel distributed sample scrambling (MPDSS)is an extension of the PDSS in which parallel sequences are generated to match the multibit-interleaved multiplexed bitstream. So, in the MPDSS, the parallel input data bitstreams are scrambled before multibit-interleaved multiplexing, and the scrambled data bitstream is descrambled after multibit-interleaved demultiplexing. In this chapter, we discuss issues involved with the multibit-parallel realizations of DSSs. We first consider how to realize the PSRGs for MPDSS along with the minimal realizations of PSRGs. Then, we examine how to achieve the multibit-parallel sampling for MPDSS along with the concurrent multibit-parallel sampling. Finally, we consider the multibit-parallel correction for MPDSS.
Byeong Gi Lee, Seok Chang Kim
Chapter 15. Three-State Synchronization Mechanism under Sample Errors
Abstract
Synchronization is a critical issue especially in the DSS since it solely relies on the transmitted samples for synchronization as opposed to the FSS case in which synchronization is achieved by resetting the shift registers to some prespecified states. The transmitted samples, however, could get corrupted by errors during transmission, while the prespecified initial state vector never gets errored. If guided by such errored samples, the DSS descrambler can not reach the synchronization state, and therefore synchronization becomes a very critical issue in the DSS.
Byeong Gi Lee, Seok Chang Kim
Chapter 16. Applications to Cell-Based ATM and High-Speed Data Networks
Abstract
We now consider how to apply the serial, parallel and multibit-parallel DSS techniques along with synchronization mechanisms we have developed in the previous chapters to scrambling in practical transmission networks. We first describe the DSS operation used in the cell-based ATM transmission for BISDN, which is the most typical lightwave transmission system employing the DSS. Then, we consider how to achieve concurrent sampling and immediate correction for eliminating additional timing circuits in this application. Also we consider how to apply the parallel DSS techniques to the cell-based ATM scrambling in conjunction with concurrent parallel sampling and immediate parallel correction. Further, we examine the synchronization mechanisms of the ATM scrambling and analyze their performances. Finally, as an extension to the ATM applications, we discuss how to design DSS scrambler and descrambler for use in future high-speed data networks.
Byeong Gi Lee, Seok Chang Kim

Self Synchronous Scrambling

Frontmatter
Chapter 17. Introduction to Self Synchronous Scrambling
Abstract
Self synchronous scrambling (SSS) is a scrambling technique which employs a kind of SRGs for use in scrambling as well as in descrambling of data bitstream. The transmission data stream is scrambled by passing through a scrambler composed of shift register generators and exclusive-OR gates, and the scrambled signal is descrambled by passing through a descrambler which is the same as the scrambler but the input and the output are reversed. In the SSS, the states of the scrambler and descrambler shift registers are automatically synchronized without any additional synchronization process. Scrambling effect of the SSS is good in general, but a bit error in the scrambled bitstream can cause multibit errors after descrambling. For the SSS, parallel scrambling techniques are available in the multiplexed environment, as for the FSS and the DSS. However, differently from these two cases, the parallel SSS (PSSS) can be applied to the parallel input signals without requiring any overlaid multiplexing frame. Instead, it requires an appropriate means to properly align the order of the descrambled parallel output signals.
Byeong Gi Lee, Seok Chang Kim
Chapter 18. Serial Self Synchronous Scrambling
Abstract
In the self synchronous scrambling (SSS), the input data bitstream controls the state of shift registers in the scrambler, and the scrambled signal controls the state of shift registers in the descrambler. We investigate these behaviors in this chapter, and examine the self-synchronization and the error-multiplication properties of the SSS. We first consider how to obtain the scrambled and the descrambled signals respectively from the input and the scrambled signals. Then, we examine how the scrambler and descrambler are automatically synchronized without any additional synchronization processing. Finally, we consider to what extent the transmission error multiplies through the self synchronous descrambling.
Byeong Gi Lee, Seok Chang Kim
Chapter 19. Parallel Self Synchronous Scrambling
Abstract
In the parallel self synchronous scrambling (PSSS), the parallel input signals are scrambled before multiplexing, and the scrambled signal is descrambled after demultiplexing, as in other parallel scrambling techniques. In this chapter, we discuss the behaviors of parallel-scrambled and parallel-descrambled signals for the SSS, and consider how to realize parallel scramblers and parallel descramblers generating these signals. We first consider the relation between the serial scrambling and the parallel scrambling, and examine the parallel-scrambled signals and the parallel-descrambled signals. Then, we mathematically model parallel scramblers and parallel descramblers, and consider how to realize them for use in the PSSS.
Byeong Gi Lee, Seok Chang Kim
Chapter 20. Applications to Scrambling in SDH-Based ATM Transmission
Abstract
In this chapter, we consider how to apply the serial and the parallel SSS techniques developed in the previous chapters to the ATM-cell scrambling in the SDH-based ATM transmission, which is the most typical lightwave transmission employing the SSS. We first describe the scrambling operations used for cell scrambling in the SDH-based ATM transmission. Then, we consider how to apply the parallel SSS techniques to the ATM-cell scrambling.
Byeong Gi Lee, Seok Chang Kim
Chapter 21. Signal-Alignment with Parallel Self Synchronous Scrambling
Abstract
The SSS has the unique property that it can scramble and descramble data sequences without looking into the internal contents of the data. Inherited from this property, the PSSS has the capability to scramble and descramble multiple base-rate signals without overlaying any frame structure. However, there is one problem appearing in this case, which is the proper distribution of the base-rate signals to their destined output lines, or the proper signal alignment. In this chapter, we consider such an signal-alignment issue in the transmission systems employing the PSSS, and discuss how to resolve the issue by employing the concept of permuting. We first represent three basic building blocks of the systems -- multiplexer, scrambler and permuter -- in terms of mathematical operators, which are directly translated into number-operators. Based on these operators, we consider how to identify the received signals in the form of a table called the signal-detection table, and examine how to characterize the signal-detection table by employing the signal-detection table characteristic expression. For various system configurations, we determine their signal-detection tables, and investigate their properties. Finally, we demonstrate how to apply the signal-detection table to the signal-alignments of the PSSS-scrambled transmission signals.
Byeong Gi Lee, Seok Chang Kim
Backmatter
Metadaten
Titel
Scrambling Techniques for Digital Transmission
verfasst von
Byeong Gi Lee, BS, ME, PhD
Seok Chang Kim, BS, ME, PhD
Copyright-Jahr
1994
Verlag
Springer London
Electronic ISBN
978-1-4471-3231-8
Print ISBN
978-1-4471-3233-2
DOI
https://doi.org/10.1007/978-1-4471-3231-8