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Erschienen in:
2013 | OriginalPaper | Buchkapitel
SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture
verfasst von : Seokjoong Kim, Matthew R. Guthaus
Erschienen in: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design
Verlag: Springer Berlin Heidelberg
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Electric devices should be resilient because reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual
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in a column-based
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memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.