Study of selective isotropic etching Si_1−xGe_x in process of nanowire transistors

On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si_1−xGe_x (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO₂, Si₃N₄ and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF₄/O₂/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si_1−xGe_x, to form cavity in advanced 3D transistor processes in future.