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2000 | OriginalPaper | Buchkapitel

Test and Testable Design

verfasst von : Hans-Joachim Wunderlich

Erschienen in: Architecture Design and Validation Methods

Verlag: Springer Berlin Heidelberg

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Defects may occur during the fabrication process and during the lifetime of integrated circuits. Integrating a faulty device into systems will result in expensive repairs or even in unsafe situations and should be avoided by testing the chipsThis section explains defect mechanisms and their consequences for the product quality. Methods for test pattern generation are discussed, and it is shown how these methods can already be supported in the design phase. Modern systems-on-chip often have the capabilities of testing themselves, and recent built-in self-test techniques (BIST) are presented.

Metadaten
Titel
Test and Testable Design
verfasst von
Hans-Joachim Wunderlich
Copyright-Jahr
2000
Verlag
Springer Berlin Heidelberg
DOI
https://doi.org/10.1007/978-3-642-57199-2_4

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