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Erschienen in:
2012 | OriginalPaper | Buchkapitel
1. The World of Metastability
verfasst von : Mohit Arora
Erschienen in: The Art of Hardware Architecture
Verlag: Springer New York
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Abstract
In a synchronous system, the data always has a fixed relationship with respect to the clock. When that relationship obeys the setup and hold requirements for the device, the output goes to a valid state within its specified propagation delay time. In synchronous systems, the input signals always meet the flip-flop’s timing requirements; therefore, metastability does not occur. However, in an asynchronous system, the relationship between data and clock is not fixed; therefore, occasional violations of setup and hold times can occur. When this happens, the output may go to an intermediate level between its two valid states and remain there for an indefinite amount of time before resolving itself or it may simply be delayed before making a normal transition.